Commit graph

136,983 commits

Author SHA1 Message Date
Mark Wang
d776d00c42 bluetooth: sbc: move sbc to bluetooth
move sbc to bluetooth because only bluetooth uses it,
change CONFIG_LIBSBC_ENCODER and CONFIG_LIBSBC_DECODER as CONFIG_LIBSBC.

Signed-off-by: Mark Wang <yichang.wang@nxp.com>
2025-12-04 05:26:00 -05:00
Mark Wang
5f79cd83ea libsbc: fix build issue
Remove `-Wno-array-bounds` as there does not seem to be any issues
that require it anymore.
Add -Wno-stringop-overflow to avoid what seem like false positive
warnings with gcc 13.3.

Signed-off-by: Mark Wang <yichang.wang@nxp.com>
2025-12-04 05:26:00 -05:00
Firas Sammoura
0119c82065 tests: riscv: Add unit tests for riscv_pmp_decode_region
This commit introduces a suite of unit tests for the `pmp_decode_region`
function using the Ztest framework. The tests validate the correct
calculation of start and end addresses for various RISC-V PMP
(Physical Memory Protection) entry configurations.

The following scenarios are covered:
- TOR (Top of Range) mode for index 0.
- TOR (Top of Range) mode for index > 0.
- NA4 (Naturally Aligned Four-byte) mode.
- NAPOT (Naturally Aligned Power-of-Two) mode.
- Default behavior for a disabled PMP entry.

These tests ensure the PMP region decoding logic is accurate across
different addressing modes.

Signed-off-by: Firas Sammoura <fsammoura@google.com>
2025-12-04 05:25:40 -05:00
Mohamed Azhar
01af640688 boards: microchip: pic32cz_ca80_cult: add pinctrl to supported list
Add pinctrl to the supported drivers list for pic32cz_ca80_cult board

Signed-off-by: Mohamed Azhar <mohamed.azhar@microchip.com>
2025-12-04 05:24:51 -05:00
Mohamed Azhar
3c79fb39a0 drivers: pinctrl: microchip: update pinctrl driver for Port G1
Updates G1 pinctrl driver

Signed-off-by: Mohamed Azhar <mohamed.azhar@microchip.com>
2025-12-04 05:24:51 -05:00
Mohamed Azhar
d90bd3a0ed dts: arm: microchip: pic32cz_ca: Add pinctrl nodes
Adds the pinctrl node and encapsulates the port nodes within
the pinctrl node for pic32cz ca series of socs, and updates
the binding file

Signed-off-by: Mohamed Azhar <mohamed.azhar@microchip.com>
2025-12-04 05:24:51 -05:00
Mohamed Azhar
f1cd357087 west.yml: Update west.yml for updating hal directory
Update west.yml for adding the pinctrl definition in
hal_microchip for pic32cz_ca devices

Signed-off-by: Mohamed Azhar <mohamed.azhar@microchip.com>
2025-12-04 05:24:51 -05:00
Seppo Takalo
7f1eb218c0 modem: pipe: Don't return EPERM on closed pipe
When working on CMUX power saving, it is typical
that we end up closing the pipe before the last
RX_READY event is handled from workqueue, so we end up
receiving -EPERM which is not really a fatal error.

Pipes recover when they are re-opened. So drop this error
and return zero instead, like modem_pipe_open() and close() does.

Signed-off-by: Seppo Takalo <seppo.takalo@nordicsemi.no>
2025-12-04 05:24:38 -05:00
Seppo Takalo
437becb0da modem: cmux: Add struct cmux_config into struct cmux
Instead of copying all fields from cmux_config into run-time
struct cmux, just have the configuration structure as a member.

Signed-off-by: Seppo Takalo <seppo.takalo@nordicsemi.no>
2025-12-04 05:24:38 -05:00
Seppo Takalo
392665578c doc: modem: Add documentation regarding CMUX power saving
Add documentation and state machine diagrams for CMUX power saving
feature and how to use it with Zephyr.

Signed-off-by: Seppo Takalo <seppo.takalo@nordicsemi.no>
2025-12-04 05:24:38 -05:00
Seppo Takalo
f6f4212710 drivers: modem: Implement support for RING indicator
Use ring indicator to wake up the CMUX device
from sleep.
Only used for runtime power management, but same event
could be used for initiating idle -> connected as well.

Signed-off-by: Seppo Takalo <seppo.takalo@nordicsemi.no>
2025-12-04 05:24:38 -05:00
Seppo Takalo
94246742fb drivers: modem: cellular: Use k_pipe instead of ringbuffer
Ringbuffer is not safe in ISR but k_pipe without waiting is.
So use pipe for events, so that possible GPIO callbacks from
ISR content can post events.

Signed-off-by: Seppo Takalo <seppo.takalo@nordicsemi.no>
2025-12-04 05:24:38 -05:00
Seppo Takalo
af0a788bd8 drivers: modem: Implement runtime power management for CMUX
CMUX driver can enable the support for idle-timer in
devicetree and can be requested to shut down the pipe
during sleep.

Then UART backend put the actual device into sleep when
pipe is closed.

Waking up is requested by sending data to DLC pipe
or by manually opening the uart_pipe.
Modem may request similar wake-up by a RING interrupt which
would open the same pipe.

When UART is powered and pipe is not closed, CMUX wake-up
procedure is automatic. Either end may initiate the wake-up.

Signed-off-by: Seppo Takalo <seppo.takalo@nordicsemi.no>
2025-12-04 05:24:38 -05:00
Seppo Takalo
aa408d7184 modem: cmux: Implement Power Saving Control message
Signal powersaving mode for the remote end using PSC command.
Wakes up the remote end from powersaving mode by sending flag characters.

This method is defined in 3GPP TS 27.010.
Sections 5.4.6.3.2 Power Saving Control (PSC) and
5.4.7 Power Control and Wake-up Mechanisms.

Essentially it is one PSC command to indicate a sleep state, and
then repeated flag characters to wake up the remote end or indicate
that we have been woken up.

Signed-off-by: Seppo Takalo <seppo.takalo@nordicsemi.no>
2025-12-04 05:24:38 -05:00
Yves Wang
3d0d909d9f doc: Update edac shell sample's readme
Update the console log in readme to make it aligned with the actual
output

Signed-off-by: Yves Wang <zhengjia.wang@nxp.com>
2025-12-04 05:24:28 -05:00
Yves Wang
e9209e60ef samples: edac: update the app to support more platforms
Decouple the edac sample with IBECC.

Signed-off-by: Yves Wang <zhengjia.wang@nxp.com>
2025-12-04 05:24:28 -05:00
Yves Wang
e0cf011c9a dts: nxp: add edac support for MCX platforms
Add eim, erm and edac instance for frdm_mcxa153, frdm_mcxn236,
frdm_mcxn947, frdm_mcxe247 and frdm_mcxe31b.

Signed-off-by: Yves Wang <zhengjia.wang@nxp.com>
2025-12-04 05:24:28 -05:00
Yves Wang
67e0217399 drivers: edac: Add NXP EDAC driver
Add edac driver for NXP's ERM and EIM peripherals. It can inject ECC
error to specific channel within EIM and then report the error address,
syndrome and count within ERM.

Signed-off-by: Yves Wang <zhengjia.wang@nxp.com>
2025-12-04 05:24:28 -05:00
Lucien Zhao
f335c00ccd boards: nxp: mimxrt700_evk: Upgrade the onboard chip to B0 silicon
- Update the pinctrl configuration for mimxrt700_evk board to support
- Update FCB settings from SDK

Signed-off-by: Lucien Zhao <lucien.zhao@nxp.com>
2025-12-04 05:24:16 -05:00
Lucien Zhao
b6868c885a manifest: hal_nxp: sync rt700 B0 chip update
Update manifest to sync rt700 B0 chip update

Signed-off-by: Lucien Zhao <lucien.zhao@nxp.com>
2025-12-04 05:24:16 -05:00
farsin NASAR V A
ec1167d78f tests: drivers: clock_control: Added sam_e54_xpro test support files
Added mchp_v1_subsys.h and sam_e54_xpro.overlay file and .conf file
Added Added sam_e54_xpro platform allow in testcase.yaml

Signed-off-by: farsin NASAR V A <farsin.nasarva@microchip.com>
2025-12-04 05:23:59 -05:00
Mathieu Choplain
aaee496010 mgmt: ec_host_cmd: backends/stm32_spi: configure proper DMA burst length
The burst length unit is bytes, not number of transfers. This had not been
an issue since the DMA driver historically ignored the values, but has now
become one since they are used and (most importantly for us) validated.

Signed-off-by: Mathieu Choplain <mathieu.choplain-ext@st.com>
2025-12-04 05:23:02 -05:00
Mathieu Choplain
3b745a1214 drivers: video: stm32_dcmi: configure proper DMA burst length
The burst length unit is bytes, not number of transfers. This had not been
an issue since the DMA driver historically ignored the values, but has now
become one since they are used and (most importantly for us) validated.

Signed-off-by: Mathieu Choplain <mathieu.choplain-ext@st.com>
2025-12-04 05:23:02 -05:00
Mathieu Choplain
4aa5e95135 drivers: uart: stm32: configure proper DMA burst length
The burst length unit is bytes, not number of transfers. This had not been
an issue since the DMA driver historically ignored the values, but has now
become one since they are used and (most importantly for us) validated.

Signed-off-by: Mathieu Choplain <mathieu.choplain-ext@st.com>
2025-12-04 05:23:02 -05:00
Mathieu Choplain
be9c5398ae drivers: i3c: stm32: configure proper DMA burst length
The burst length unit is bytes, not number of transfers. This had not been
an issue since the DMA driver historically ignored the values, but has now
become one since they are used and (most importantly for us) validated.

Signed-off-by: Mathieu Choplain <mathieu.choplain-ext@st.com>
2025-12-04 05:23:02 -05:00
Mathieu Choplain
9e14885e14 drivers: i2s: stm32: configure proper DMA burst length
The burst length unit is bytes, not number of transfers. This had not been
an issue since the DMA driver historically ignored the values, but has now
become one since they are used and (most importantly for us) validated.

Signed-off-by: Mathieu Choplain <mathieu.choplain-ext@st.com>
2025-12-04 05:23:02 -05:00
Mathieu Choplain
f3499071cd drivers: i2c: stm32: configure proper DMA burst length
The burst length unit is bytes, not number of transfers. This had not been
an issue since the DMA driver historically ignored the values, but has now
become one since they are used and (most importantly for us) validated.

Signed-off-by: Mathieu Choplain <mathieu.choplain-ext@st.com>
2025-12-04 05:23:02 -05:00
Mathieu Choplain
c4d884c7ed drivers: adc: stm32: configure proper DMA burst length
The burst length unit is bytes, not number of transfers. This had not been
an issue since the DMA driver historically ignored the values, but has now
become one since they are used and (most importantly for us) validated.

Signed-off-by: Mathieu Choplain <mathieu.choplain-ext@st.com>
2025-12-04 05:23:02 -05:00
Mathieu Choplain
208b3ef5ba drivers: spi: stm32: configure proper DMA burst length
The burst length unit is bytes, not number of transfers. This had not been
an issue since the DMA driver historically ignored the values, but has now
become one since they are used and (most importantly for us) validated.

Fixes broken 16-bit on STM32N6 series.

Signed-off-by: Mathieu Choplain <mathieu.choplain-ext@st.com>
2025-12-04 05:23:02 -05:00
Mathieu Choplain
3e64d53b17 release-notes: 4.4: add new voltage-scale property for STM32U5 PWRC
Add new voltage scale selection property for STM32U5 to 4.4 release notes.

Signed-off-by: Mathieu Choplain <mathieu.choplain-ext@st.com>
2025-12-04 05:22:26 -05:00
Mathieu Choplain
926f9f456b drivers: clock_control: stm32u5: fix frequency range check for scale
The range check should be inclusive: scale 4 allows *up to* 25 MHz, scale 3
*up to* 55 MHz, etc.

Signed-off-by: Mathieu Choplain <mathieu.choplain-ext@st.com>
2025-12-04 05:22:26 -05:00
Mathieu Choplain
1f70c795c7 drivers: clock_control: stm32u5: add configurable voltage scale support
Add support for the new `voltage-scale` property on the STM32U5-specific
Power Controller binding.

Signed-off-by: Mathieu Choplain <mathieu.choplain-ext@st.com>
2025-12-04 05:22:26 -05:00
Mathieu Choplain
6dd9182912 dts: arm: st: stm32: u5: add U5-specific compatible on Power Controller
Add the "st,stm32u5-pwr" compatible to the Power Controller node in the
DTSI for STM32U5 series.

Signed-off-by: Mathieu Choplain <mathieu.choplain-ext@st.com>
2025-12-04 05:22:26 -05:00
Mathieu Choplain
a49a06949c dts: bindings: pwr: add STM32U5 power controller binding
Add a binding for the power controller of STM32U5 series.

Signed-off-by: Mathieu Choplain <mathieu.choplain-ext@st.com>
2025-12-04 05:22:26 -05:00
Michał Stasiak
46e90f93f5 soc: nordic: nrf_sys_event: handle errors correctly
nrfx_power_constlat API returns negative value if
the requested action has no effect, which is expected
in cases of multiple requests/releases. Align nrf_sys_event
to not treat it as an error.

Signed-off-by: Michał Stasiak <michal.stasiak@nordicsemi.no>
2025-12-04 05:21:55 -05:00
Sai Santhosh Malae
ef1bd9d2a9 samples: adc: siwx91x: Add adc_dt support for siwx917_rb4338a
Add an overlay to enable the adc_dt sample on the siwx917_rb4338a
board.

Signed-off-by: Sai Santhosh Malae <Santhosh.Malae@silabs.com>
2025-12-04 05:21:40 -05:00
Sai Santhosh Malae
78f47a362f drivers: adc: siwx91x: Return raw ADC value
Instead of returning a converted ADC reading, return the
raw ADC sample. Conversion is left to the user based on
the selected ADC mode (single-ended or differential).

Signed-off-by: Sai Santhosh Malae <Santhosh.Malae@silabs.com>
2025-12-04 05:21:40 -05:00
Sai Santhosh Malae
f4c152ab47 drivers: adc: siwx91x: Add ref_internal to device API
The Siwx91x ADC reference voltage is configurable rather than fixed.
Expose `ref_internal` in the device API so the driver can retrieve the
reference voltage from the device tree instead of assuming a constant
value.

Signed-off-by: Sai Santhosh Malae <Santhosh.Malae@silabs.com>
2025-12-04 05:21:40 -05:00
Alvis Sun
55156419bc drivers: sensor: npcx: add sensor v2t support for npck3
Introduces the sensor driver managing the V2T module for
temperature readout.

Signed-off-by: Alvis Sun <yfsun@nuvoton.com>
2025-12-04 05:21:24 -05:00
Alvis Sun
e69bbfc55c drivers: adc: npcx: add-v2t support for npck3
Please note that when performing conversions,
the selected channels must all be of the same type
(either ADC raw or V2T.)

Mixing ADC and V2T channels in a single conversion sequence is
not supported.

Signed-off-by: Alvis Sun <yfsun@nuvoton.com>
2025-12-04 05:21:24 -05:00
Alvis Sun
b4a9e6f0b6 drivers: adc: npcx: add adc driver support for npck3
As title.

Signed-off-by: Alvis Sun <yfsun@nuvoton.com>
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
2025-12-04 05:21:24 -05:00
S Mohamed Fiaz
57a2249896 boards: silabs: siwx91x: Fix MEMC enable and initialization priorities
This commit corrects board configuration to enable the memory controller
and set proper initialization priorities, ensuring PSRAM is correctly
initialized during system startup.

Signed-off-by: S Mohamed Fiaz <Fiaz.Mohamed@silabs.com>
2025-12-04 05:20:20 -05:00
Rex Chen
64a1477976 modules: hostap: Fix connection failed with TLS cipher RSA3K
The TLS cipher RSA3K ciphersuites ECDHE-RSA-AES256-GCM-SHA384 and
DHE-RSA-AES256-GCM-SHA384 only support TLS1.2, but TLS1.3 enabled,
version check failed in ssl_tls13_validate_peer_ciphersuite
during parse client hello.
Disable TLS1.3 for TLS cipher RSA3K to fix this issue.

Signed-off-by: Rex Chen <rex.chen_1@nxp.com>
2025-12-04 06:34:58 +00:00
Peter Mitsis
0d4856bb38 tests: Fix variable name
Updates the spawn_threads() sleep_sec parameter name to sleep_msec
to more accurately reflect the units of measurement.

Signed-off-by: Peter Mitsis <peter.mitsis@intel.com>
2025-12-04 06:34:47 +00:00
Maureen Helm
e76dd0c7ec dts: bindings: usb: Fix max3421e compatible to use hyphen word separator
Fixes the max3421e devicetree compatible to follow the convention of
using a hyphen rather than an underscore as the word separator.

Signed-off-by: Maureen Helm <maureen.helm@analog.com>
2025-12-04 06:34:09 +00:00
Nicholas Lowell
d98ec13320 logging: add all format options to Kconfig and std_get_flags()
Some but not all LOG_OUTPUT_ format flags were Kconfigurable
for log backends using log_backend_std_get_flags()

Adding the missing configurable flags to Kconfig and referencing
them in log_backend_std_get_flags() for full control of output:
- CRLF_NONE
- CRLF_LFONLY
- SKIP_SOURCE

FORMAT_SYSLOG was omitted b/c it is specific to NET log backend.

Signed-off-by: Nicholas Lowell <Nicholas.Lowell@lexmark.com>
2025-12-04 06:33:40 +00:00
Sylvio Alves
d14a547d42 dts/dtsi: add missing zephyr prefix for consistency
Many dts/dtsi files where its dt-bindings are in-tree
do not include zephyr prefix in the #include path.
Add it to make it consistent globally.

Some dt-bindings that resides in hal can not be changed.

Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
2025-12-03 15:38:17 -05:00
Holt Sun
6cacb70092 soc: nxp: lpc55XXX: add cache support for LPC55S36
Enable instruction cache support for LPC55S36 SoC:
- Select CPU_HAS_ICACHE and HAS_MCUX_SYSCON_LPCAC
- Enable CACHE_MANAGEMENT and EXTERNAL_CACHE by default
- Set ICACHE_LINE_SIZE to 256 bytes

This enables the SYSCON LPCAC cache driver for improved
performance on the LPC55S36 SoC.

Signed-off-by: Holt Sun <holt.sun@nxp.com>
2025-12-03 15:37:50 -05:00
Holt Sun
aa6f7e925b modules: hal_nxp: add SYSCON LPCAC cache support
Add HAL support for SYSCON LPCAC cache controller by:
- Adding HAS_MCUX_SYSCON_LPCAC Kconfig option
- Integrating cache_lpcac_mcxn driver component

Signed-off-by: Holt Sun <holt.sun@nxp.com>
2025-12-03 15:37:50 -05:00
Holt Sun
b403bb5c66 drivers: cache: add NXP SYSCON LPCAC cache driver
add cache driver for NXP SYSCON LPCAC controller,
this driver provides instruction cache management
with enable/disable and invalidation support.

Signed-off-by: Holt Sun <holt.sun@nxp.com>
2025-12-03 15:37:50 -05:00