Due to multiple customer requests we are deprecating the MEC5 HAL.
Customers prefer all code to be in the main Zephyr tree. They do
not want a dependency on an outside SoC HAL. These changes remove
the MEC5_HAL select from MEC165xB, MEC174x, and MEC175x. The SoC
code calling the HAL for debug configuration was replaced with
a small amount of code common to all SoC's. We also moved all
the common header includes into a common SoC header to prevent
changing multiple files if new common headers are added.
Note: the in-tree drivers: kernel timer, GPIO, PINCTRL, and UART
are all non-HAL.
Signed-off-by: Scott Worley <scott.worley@microchip.com>
In sensor_shell_stream.c, cmd_sensor_stream() checks for valid trigger
types, but it is missing SENSOR_TRIG_TIMER option.
Signed-off-by: Brandon Edmonds <bedmonds91@gmail.com>
The K_TIMEOUT_SUM() macro is intended as a means to add two
k_timeout_t values together. This may be useful for a developer
applying an exponential backoff algorithm.
Signed-off-by: Peter Mitsis <peter.mitsis@intel.com>
- Add SPI driver for Microchip SERCOM g1
- Add and update Kconfig files to support the driver
- Update CMakeLists.txt to include the new driver
Signed-off-by: Mohamed Azhar <mohamed.azhar@microchip.com>
Modifies sample application to use error callback mechanism added to
haptics API instead of device-specific API extension.
Signed-off-by: Liam Ogletree <liam.ogletree@cirrus.com>
Modifies the CS40L5x driver to use the error callback mechanism
added to the haptics API instead of a device-specific API
extension.
Signed-off-by: Liam Ogletree <liam.ogletree@cirrus.com>
Haptics devices provide protection features to prevent damage during
operation. Adds an error callback mechanism to the haptics API to
enable haptics device drivers to raise these conditions to the
application layer. Enumerates a subset of errors that are common
to modern haptics devices across major vendors.
Signed-off-by: Liam Ogletree <liam.ogletree@cirrus.com>
This patch just formats the uart_xmc4xxx.c file before the real
patch, otherwise the changes would be hard to read.
Signed-off-by: Marcelo Roberto Jimenez <marcelo.jimenez@gmail.com>
The current PMS7003 sensor driver in Zephyr only supports reading the
basic PM1.0, PM2.5, and PM10 concentration values.
This update extends the driver to support additional data provided by the
PMS7003 sensor, including:
- Standard particle concentration values (CF=1) for PM1.0, PM2.5, and PM10
- Particle counts for particles greater than or equal to 0.3 µm, 0.5 µm,
1.0 µm, 2.5 µm, 5.0 µm, and 10.0 µm per 0.1 liter of air
Adding support for these readings allows applications to access more
detailed particulate data, improving the sensor’s usability in air quality
monitoring and analysis scenarios.
Signed-off-by: Hanan Arshad <hananarshad619@gmail.com>
When the USB Bus is reset, the USBD stack will disable and re-enable
all Classes. If this occurs while streaming audio with UAC2, the
terminals remain active when re-enabled, yet the endpoints have
yet to be enabled (resulting in -ENODEV logspam). This change
disables all active terminals when the class is disabled.
Signed-off-by: Victor Brzeski <vbrzeski@gmail.com>
Add test and sample overlays for CY8CKIT-041S-MAX board:
- GPIO basic API test using P1.2 and P1.3 pins
- Button sample using P11.5 with pull-up configuration
Signed-off-by: Braeden Lane <Braeden.Lane@infineon.com>
Add support for Infineon CY8CKIT-041S-MAX development kit
based on CY8C4149AZI-S598 (PSoC 4100S Max).
Board features:
- 100-pin TQFP PSOC 4100S Max MCU (384KB Flash, 32KB SRAM)
- User LED and button
- KitProg3 for programming/debugging
- Common dtsi structure for peripheral configuration
Signed-off-by: Braeden Lane <Braeden.Lane@infineon.com>
Add clock control and UART support for PSOC 4 family:
- Clock control drivers with PSOC 4 compatibility
- PSOC4xx clock source bindings and definitions
- HF clock divider configuration support
- UART FIFO trigger level configuration for PSOC 4100S Max
series with 8-deep FIFO (RX trigger=7, TX trigger=0)
Signed-off-by: Braeden Lane <Braeden.Lane@infineon.com>
Add devicetree support for PSOC 4100S Max series including:
- Base SoC dtsi with GPIO, UART, HSIOM peripherals
- 100-TQFP package dtsi for pin multiplexing
- CY8C4149AZI-S598 MPN-specific devicetree include
- Updated compatible strings for PSOC 4 support
- Clock structure with clk_hf and clk_pump nodes
- Simplified peripheral clock naming (peri_clk_div)
- PSOC4xx clock source definitions and bindings
Signed-off-by: Braeden Lane <Braeden.Lane@infineon.com>
Add initial support for the PSOC 4100S Max series, starting
with the CY8C4149AZI-S598 (100-TQFP package) used on the
CY8CKIT-041S-MAX development board.
The infrastructure supports adding additional part numbers
in the future as needed.
Signed-off-by: Braeden Lane <Braeden.Lane@infineon.com>
Add early len check, remove use of strcpy, strncpy and
strncmp.
Co-authored-by: Emil Gydesen <emil.gydesen@nordicsemi.no>
Signed-off-by: Vinayak Kariappa Chettimada <vich@nordicsemi.no>
Fix truncation detection after strncpy, as strlen cannot be
used if the src was truncated due to insufficient size of
dst.
Signed-off-by: Vinayak Kariappa Chettimada <vich@nordicsemi.no>
Rework settings implementation for not reusing the OS
snprintk implementation with CONFIG_PRINTK=n and to return
error if path buffer is insufficient.
Signed-off-by: Vinayak Kariappa Chettimada <vich@nordicsemi.no>
Rework settings implementation for not reusing the OS
snprintk implementation with CONFIG_PRINTK=n.
Signed-off-by: Vinayak Kariappa Chettimada <vich@nordicsemi.no>
Update settings implementation for not reusing the OS
snprintk implementation with CONFIG_PRINTK=n.
Signed-off-by: Vinayak Kariappa Chettimada <vich@nordicsemi.no>
- Add a new test configuration file enabling RTC calibration and alarm
features for the nucleo_u385rg_q board
- Add the nucleo_u385rg_q device tree overlay defining the RTC alias
Signed-off-by: Antoine Pradoux <antoine.pradoux@st.com>
- Activate the RTC node in the device tree by enabling its clocks and
setting its status to okay
- Add 'rtc' to the supported features in the board YAML configuration
Signed-off-by: Antoine Pradoux <antoine.pradoux@st.com>
Extend RTC driver to handle STM32U3 series specifics:
- Include STM32U3X in condition where RTC Alarm event is not routed to EXTI
- Use LL_RCC_RTC_ClockEnable call for STM32U3 instead of LL_RCC_EnableRTC
- Adapt counter_stm32_rtc driver for STM32U3 clock and EXTI handling
Signed-off-by: Antoine Pradoux <antoine.pradoux@st.com>
- Add the rtc node for the stm32u3
- This enables RTC support for STM32U3 platforms once enabled
Signed-off-by: Antoine Pradoux <antoine.pradoux@st.com>
Change the toolchain version resolution order to check for
board-specific TOOLCHAIN_VER_${NORMALIZED_BOARD_TARGET} first,
falling back to the generic TOOLCHAIN_VER if not defined.
Now if we want to use various boards lots of them uses same version
but fewer ones differ. We won't have to define TOOLCHAIN_VER for
every board.
Signed-off-by: Anil Ozrenk <anil.ozrenk@analog.com>
The JEDEC ID for the Winbond W25Q64JV flash on the MCX NX4X EVK board
was incorrectly specified as [ef 40 17]. According to the W25Q64JV
datasheet, the correct JEDEC ID is [ef 60 17], where:
- ef: Winbond manufacturer ID
- 60: Memory type (W25Q series)
- 17: Capacity (64 Mbit)
Update the jedec-id property to match the actual flash device.
Signed-off-by: Albort Xue <yao.xue@nxp.com>
The JESD216_DW15_QER_VAL_S2B1v5 case had incorrect status register
read/write logic. It was reading only SR2 but writing both SR1 and SR2,
which could corrupt SR1 if not read first.
Merge the S2B1v5 case with S2B1v1/v4 cases since they all set bit 1 of
SR2. Update the common path to properly handle both single-byte (SR2 only)
and two-byte (SR1+SR2) read/write operations by:
- Reading SR1 first when rd_size is 2, saving it temporarily
- Reading SR2 using the scratch command
- Combining both bytes with SR2 in the upper byte when needed
- Writing the combined value with the QE bit set
Remove the now-redundant S2B1v5-specific case and simplify the LUT
sequence to read SR2 directly instead of reading SR1 first.
Signed-off-by: Albort Xue <yao.xue@nxp.com>
The remain_on_channel callback triggers cookie_event, which checks
pending_remain_on_channel before giving drv_resp_sem. Previously,
pending_remain_on_channel was set after calling
dev_ops->remain_on_channel, causing drv_resp_sem to timeout.
Move the pending_remain_on_channel assignment before invoking
dev_ops->remain_on_channel to ensure proper synchronization.
Signed-off-by: Maochen Wang <maochen.wang@nxp.com>
Remove local Tx buffer allocated in the
bt_hci_stm32wba_send() function.
Get Event buffer resource to store data returned
by lower layer and provide it to Host in case of
Tx packet is an HCI Command type.
Signed-off-by: Vincent Tardy <vincent.tardy@st.com>
- There was a mistake with the CM33 core. It does
not have ITCM/DTCM. Only the CM55 core does.
- Also enabled ITCM/DTCM in the cm55 board file.
Signed-off-by: Bill Waters <bill.waters@infineon.com>
Document that TLS version passed to a zsock_socket() function is no
longer ignored and is now enforced as the minimum TLS version for the
TLS session.
Signed-off-by: Robert Lubos <robert.lubos@nordicsemi.no>
Document explicitly that the TLS version passed in the protocol
parameter matters and specifies the minimum TLS version to use for the
socket.
Signed-off-by: Robert Lubos <robert.lubos@nordicsemi.no>
Enforce the minimum TLS version on mbed TLS, based on the protocol
version provided by the application when creating socket. This ensures
that when application creates a TLS 1.3 socket, mbed TLS won't downgrade
the session to TLS 1.2 for instance.
Signed-off-by: Robert Lubos <robert.lubos@nordicsemi.no>
