Add bindings for the SF32LB52X SoCs PINMUX peripheral. Note that
SF32LB56X SoCs contain a compatible IP (not others, where HPSYS_CFG is
not required), so if SF32LB56X support is added, binding could be
adjusted to reflect 52x/56x support.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
Initial driver for SF32LB SoCs. This driver is incomplete, but allows
to configure the system for a minimal boot.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
This is defined as a subnode because RCC is a MFD device (clock and
reset controller), however, Zephyr does not allow >1 device per DT node!
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
Add bindings for the SiFli SF32LB PMUC. PMUC is a sort of "syscon" type
register block used to control multiple power-management related stuff.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
Refer to Ch 2 "Clock and Reset" from reference manual. Some may require
specific bindings in the future if they can be configured (e.g. RC48).
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
SiFli SF32LB AON module controls certain low-power or clocks, e.g.
enablement of HXT48 on different LP modes, etc.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
SiFli SoCs have a multi-purpose register set named HPSYS_CFG, which we
can treat as a "syscon".
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
This brings CMSIS HAL glue code, which is required if we want to enable
any HAL module without everything blowing up. cmsis_core_m_defaults.h
cannot be used once we enable HAL. CMSIS is that nice.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
Add glue code to build SiFli HAL. The bare minimum is included, some
more things may be required as we fully test the integration in the
future.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
Add SiFli HAL module. This module contains register-level description
for SF32LB SoCs IP, and a high-level HAL.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
SF32LB52x is a SoC from SiFli Technologies(Nanjing) Co., Ltd, based on
Arm Star-MC1 core (Cortex-M33 compatible).
For more details, see:
https://wiki.sifli.com/en/hardware/SF32LB520-3-5-7-HW-Application.htmlhttps://wiki.sifli.com/en/hardware/SF32LB52B-E-G-J-HW-Application.html
0-3-5-7 are powered using a Lithium battery and support USB charging.
B-E-G-J are powered at 3.3V and do not support charging.
Other termination codes indicate what type of memory and size is
embedded in the package (QSPI NOR or PSRAM).
Other families exist within the SF32LB family, like SF32LB56x,
SF32LB58x, etc.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
SRAM is segmented as:
- RAM0: 128K (DTCM)
- RAM1: 128K
- RAM2: 256K
where:
- RAM0 can be accessed by all peripherals except PTC1/2.
- RAM1/RAM2 have its own port, so e.g. master 1 can access RAM1 while
master 2 can access RAM2.
Depending on the application, one may decide to just use the whole RAM
as a single block, split RAM0 (DTCM) and RAM1/2, etc. For now, provide 2
schemes:
- Use all SRAM as a single block
- Use RAM0 (DTCM) + RAM1/2
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
Just define basic ARM hardware: CPU, MPU and NVIC settings. SF32LB SoCs
are technically Arm-Star MC1 based, an Arm Cortex-M33 compatible CPU
developed by Arm China.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
The k_event event is only used if CONFIG_PM_DEVICE_RUNTIME_ASYNC is
selected, but EVENTS is selected, and the k_event included in the
struct pm_device if CONFIG_PM_DEVICE_RUNTIME is selected.
Correct to only include event and EVENTS if
CONFIG_PM_DEVICE_RUNTIME_ASYNC is selected. This saves us 1
struct event per PM DEVICE.
Signed-off-by: Bjarki Arge Andreasen <bjarki.andreasen@nordicsemi.no>
A follow up to commit 78c1def4db that
probably missed this file.
Fixes CI issues observed in weekly run:
- kincony_kc868_a32/esp32/procpu:libraries.devicetree.api_ext
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
Add missing `.key` designator.
This also fixes a compile error:
> error: either all initializer clauses should be designated or none of
them should be
Signed-off-by: Jeppe Odgaard <jeppe.odgaard@prevas.dk>
Add all the `West project: trusted-firmware-m` collaborators to
`tf-m-tests` and `psa-arch-tests`. They are repositories highly related
to TF-M.
Signed-off-by: Tomi Fontanilles <tomi.fontanilles@nordicsemi.no>
This commit should deal with updating the maintainers list for Smartbond
family of devices.
Signed-off-by: Ioannis Karachalios <ioannis.karachalios.px@renesas.com>
Gitlint-core has loose requirements and not conflicting
with scancode-toolkit v32.4.1 (click==8.1.3 vs click>=8.2.0).
Signed-off-by: Nicolae Dicu <nicolae.dicu@nordicsemi.no>
Currently, the DMA on several Renesas boards is failing due to
the security attribution of DMA.
As a solution: Enable secure security attribution
for DMA module for:
- RA6: ra6e1, ra6e2, ra6m4, ra6m5
- RA4: ra4c1, ra4e1, ra4e2, ra4l1, ra4m2, ra4m3
Signed-off-by: Khanh Nguyen <khanh.nguyen.wz@bp.renesas.com>
Signed-off-by: Khoa Nguyen <khoa.nguyen.xh@renesas.com>
Use `collections.defaultdict` to simplify code, and use the `bytes`
type internally rather than hex strings.
Signed-off-by: Jordan Yates <jordan@embeint.com>
NPCX7, NPCX9, and NPCK3 platforms have their (NUM_IRQS-1) IRQ taken,
so set CONFIG_TEST_IRQ_NUM to a different available IRQ.
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
This aims to implement a packet forwarding mechanism between
DNS resolver and applications that install a callback, letting
DNS resolver know that received UDP packet is also required by an
application.
Signed-off-by: Cristian Bulacu <cristian.bulacu@nxp.com>
The NRF_802154_ENCRYPTION was split into two additional Kconfigs that
control separate functionalities:
* NRF_802154_IE_WRITER - to enable Information Element writer
* NRF_802154_SECURITY_WRITER - to enable frame counter writer
Signed-off-by: Rafał Kuźnia <rafal.kuznia@nordicsemi.no>
Explicitly set the default alt clock for canfd. Without
explicitly setting it the clock subsystem will return
the frequency of the gating clock(APB1).
Signed-off-by: Thomas Stranger <thomas.stranger@outlook.com>
Fix peripheral availability per h5 line.
Some peripherals are not available on the entry level
lines of the stm32h5 series:
- fdcan2 only on SoCs >= H523, but not on h562
- sai only on >= H562
- ethernet only on >= H563
Signed-off-by: Thomas Stranger <thomas.stranger@outlook.com>
Since we're not yet at a consensus on where 'write-block-size' should be
set, make the adjustable alignment expected only in the revert case
to restore functionality on the 'normal' case.
Signed-off-by: Erwan Gouriou <erwan.gouriou@st.com>
Enable the LPM013M126A display node under USART1 in the slstk3701a DTS.
Add pre_dt_board.cmake to suppress SPI bus bridge warnings, and update the
pinctrl configuration to properly configure the display control pins.
Signed-off-by: Elgin Perumbilly <elgin.perumbilly@siliconsignals.io>
