On i.MX 93 platform, no need to clear interrupt flags, otherwise it
will not trigger reset.
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Signed-off-by: Joe Zhou <zhongcai.zhou@nxp.com>
Linkeserver should be the default runner because that's actually what
comes on the board out of box, which is already indicated in the
documentation of the board.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
As discussed on Discord, certain k_mem_slab* APIs are ISR-OK, but not
marked as such. After APIs review, the following functions should be
ISR-OK:
- k_mem_slab_free
- k_mem_slab_num_used_get
- k_mem_slab_max_used_get
- k_mem_slab_num_free_get
- k_mem_slab_runtime_stats_get
- k_mem_slab_runtime_stats_reset_max
Added the Doxygen marker where needed.
Signed-off-by: Loic Domaigne <tech@domaigne.com>
This removes the special test case for intel_adsp to skip
the mapped code execution test. The test can now run on
the ACE3.0 hardware without issue.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
The mapped code execution test uses the simple k_mem_phys_addr()
to do virtual to physical address translation. And this requires
the virtual address to be inside the kernel permanent mapping
(i.e. between __kernel_ram_start and __kernel_ram_end). With
demand paging, the translation is no longer static and it can be
mapped into any physical address. So a simple memory mapping
in the test would map an incorrect physical address which may
not even contain the said function. It has been working when
demand paging is not enabled is due to the custom sections is
immediately after the text section, so that the simple address
translation still works. But a custom linker script (i.e. board
config) may make that not true anymore.
So fix this by putting transplanted_function() into
snippets-text-sections.ld such that this would appear inside
.text section.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Adds snippets-text-sections.ld to ACE linker scripts.
For now, this is for the memory mapping test.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Adds snippets-text-sections.ld to arm/cortex_a_r and arm64
linker scripts.
For now, this is for the memory mapping test.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Adds snippets-text-sections.ld to x86 linker scripts.
For now, this is for the memory mapping test.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
1. Fix an off-by-one error in `signo_fits()` (a utility function inside
signal.c
2. Adjust expectations for C libraries that do not provide a sigset_t
large enough to support `SIGRTMIN` or `SIGRAMAX`.
This fixes an issue in CI that appeared when run under ARC.
```shell
west build -p auto -b qemu_arc/qemu_arc_hs -t run tests/posix/signals
```
Signed-off-by: Chris Friedt <cfriedt@tenstorrent.com>
Extend the LIS2DU12 accelerometer driver with SENSOR_TRIG_DELTA
support. The detection is based on the slope between successive
channel readings. Support for setting SENSOR_ATTR_SLOPE_TH and
SENSOR_ATTR_SLOPE_DUR is added as well. In line with other sensors,
SENSOR_ATTR_SLOPE_TH is configured in SI units (m/s^2) and
SENSOR_ATTR_SLOPE_DUR in samples relative to the ODR. The new trigger
can be mapped either to the same GPIO as the data-ready interrupt or
to a dedicated one.
Signed-off-by: Jan Kablitz <jan.kablitz@8tronix.de>
Add basic testing to validate the API of the NVMEM subsystem.
Add testing with an EEPROM backend.
Signed-off-by: Pieter De Gendt <pieter.degendt@basalte.be>
This commit adds the NVMEM subsystem with a basic implementation for use
with EEPROM devices.
Signed-off-by: Pieter De Gendt <pieter.degendt@basalte.be>
Adds property nvmem-cells for referencing a node that stores some
configuration information. A typical use case is the reading of MAC
address from an EEPROM device.
Signed-off-by: Andriy Gelman <andriy.gelman@gmail.com>
Signed-off-by: Pieter De Gendt <pieter.degendt@basalte.be>
Configure i3c1 nodes on stm32n6570_dk.
Note that pins conflict with i2c1 ones, so don't enable it here and
it will have to be enabled by application
Signed-off-by: Erwan Gouriou <erwan.gouriou@st.com>
Updates the smp test to support nsim/nsim_hs5x/smp/12cores.
Furthermore, if someone attempts to build the smp test for more
than 12 CPUs, report an error message informing the user to
reduce the number of CPUs. This reduction can be in the form
of a custom overlay for the board in question.
Fixes#96339
Signed-off-by: Peter Mitsis <peter.mitsis@intel.com>
This commit adds an entry in MAINTAINERS.yml for the Instrumentation
Subsystem added in #91595.
Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
This commit moves the `zaru.py` script to `scripts/instrumentation`, and
adjusts references to the script in other places.
Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
ElemRV-N has a gpio controller. Enable this node in the board-level
device-tree and add this interface to all aux. files.
Also sort device-tree nodes in the DTS file alphabetically.
Signed-off-by: Daniel Schultz <dnltz@aesc-silicon.de>
Add basic support for the Aesc Silicon GPIO controller.
This IP core has internal tri-states and therefore a read,
write and direction registers. Additionally, it has advanced
monitoring capabilities for interrupt generation; low or
high leve and rising or falling edge.
Interrupt support will be added later when ElemRV supports
interrupt in Zephyr.
Signed-off-by: Daniel Schultz <dnltz@aesc-silicon.de>
Change the ISR code to return once all pended interrupts
are handled instead of continuing to iterate over
all channels. Common occurence is just for one interrupt
bit to be set so no need to check all bits in all channels
if only one bit is pending.
Signed-off-by: Mike J. Chen <mjchen@google.com>
Handle notification interrupt before data interrupt of
a channel. Notification interrupts are more commonly
used (e.g. for ipc) and clearing the interrupt ASAP
helps reduce the possiblility that the sender finds
the interrupt already pending if it tries to send multiple
ipc messages in quick succession.
Signed-off-by: Mike J. Chen <mjchen@google.com>
Handle all interrupts for a channel before going to next
channel. Previous code did an if/else check, so if both
a data rx interrupt and a notification interrupt were pending
for a channel, only one would be handled in the ISR. The
ISR would have to fire again (probably would be still pending)
for the other interrupt to be processed. This could even
lead to starvation/delay if another data rx interrupt got
pended again.
Signed-off-by: Mike J. Chen <mjchen@google.com>
Change to pass the device node to IRQ_CONNECT and remove
the intermediate interrupt handler that has to call
DEVICE_DT_INST_GET() to get the device pointer.
Signed-off-by: Mike J. Chen <mjchen@google.com>
The ipc backends, like icmsg.c, don't expect errors when
using mailbox send for notifications. In some places,
icmsg.c ignores the return value of the mailbox send,
in some places it propagates the error up, and in some
places it asserts.
icmsg only uses the mailbox send with NULL msg as a means
to interrupt the other processor, and all data is passed
via shared memory. So it is safe to ignore the case when
the interrupt is already pending, since the other
processor should handle the pending message when it gets
around the handling the interrupt. As long as the order
of clearing the interrupt is before the handling of the
data, there should be no case where not pending a new
interrupt when one is already pending would result in missing
any new message.
Signed-off-by: Mike J. Chen <mjchen@google.com>
Add support for WeAct Studio ESP32-S3-B development board featuring:
- ESP32-S3R8 chip with 8MB integrated PSRAM
- 16MB external SPI flash
- RGB WS2812 LED on GPIO48
- User button on GPIO45
- Dual USB-C connectors
- Wi-Fi and Bluetooth LE support
Signed-off-by: Siratul Islam <sirat4757@gmail.com>
There were some corner cases and stress test could fail. Reworking
tail bits handling to make the stress test pass.
Signed-off-by: Krzysztof Chruściński <krzysztof.chruscinski@nordicsemi.no>
GRTC is used by the logger, so it must be initialized
as early as possible. On the other hand, clock requests
are allowed once the clock control API has been initialized.
This PR introduces a two-stage GRTC initialization to meet
these requirements.
Signed-off-by: Adam Kondraciuk <adam.kondraciuk@nordicsemi.no>
hal_silabs now includes the last version (3.5.2) of WiseConnect, the
downstream SDK for Silicon Labs SiWx91x series.
Signed-off-by: Jérôme Pouiller <jerome.pouiller@silabs.com>
Align with native_simulator's upstream main
4641dad899979528e4083aa762651388a2a7ec7b
Which includes:
4641dad common: nsi_internal.h: Use NSI_INLINE macros
7a1156c nsi_tasks: move header to include folder
6b7d76a nct: fix restarting sem_wait after signal
166516d nce: fix restarting sem_wait after signal
Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
