This patch just formats the file before the real patch so that
whitespace changes do not mix with the real code changes.
Signed-off-by: Marcelo Roberto Jimenez <marcelo.jimenez@gmail.com>
Commit 539928d introduced a special behaviour for Microchip QSPI flash
memories into the STM32 QSPI flash driver, to handle the fact that these
memories use the PP_1_1_4 opcode (32H) for the PP_1_4_4 operation
(usually 38H).
The special Microchip-specific behaviour introduced in that commit sets
the address mode for a QSPI 1-1-4 write operation to 4 address lines,
rather than 1 address line, when the write command is configured as
SPI_NOR_CMD_PP_1_1_4. If the write command is configured as
SPI_NOR_CMD_PP_1_4_4, nothing is done and the operation will not succeed.
This behaviour is a bit backwards, as it results in a QSPI flash memory
configured in 1-1-4 write mode using 4 address lines (1-4-4 operation).
It should be the other way round, so that a QSPI flash memory configured
in 1-4-4 mode uses 4 address lines (1-4-4 operation).
This commit changes the Microchip-specific special behaviour to set the
opcode for the specified write mode, rather than using a different write
mode to that which is configured in order to use a valid opcode. This
means that a QSPI flash memory configured in 1-4-4 mode, or without the
writeoc DT property set (defaults to 1-4-4 for quad mode), will operate
in 1-4-4 mode. 1-1-4 mode is unsupported, as before.
Also update the Kconfig option description for
CONFIG_USE_MICROCHIP_QSPI_FLASH_WITH_STM32 to remove references to the
Global Block Protection Unlock instruction - this was added at the same
time as the Microchip-specific special behaviour for the 1-1-4 / 1-4-4
opcode but is distinct from this and is not affected by
CONFIG_USE_MICROCHIP_QSPI_FLASH_WITH_STM32.
Signed-off-by: Ben Marsh <ben.marsh@helvar.com>
Add support for the touch input controller on the STM32H7S78-DK:
- Enable I2C1 on the board
- Add device tree node for the touch controller in the display panel
Signed-off-by: Titouan Christophe <titouan.christophe@mind.be>
Added three functions to support the EAD peripheral:
- Setting and storing key materials for EAD
- Encrypting data for EAD advertisements
- Decrypting data from EAD advertisements
Signed-off-by: Petri Pitkanen <petri.pitkanen@silabs.com>
The PMP initialization and thread seeding logic in arch/riscv/core/pmp.c
did not correctly handle scenarios where the global PMP entries span
across multiple `pmpcfg` hardware registers.
The `global_pmp_cfg` array, intended to store the hardware register
values, was hardcoded to size 1. This is only sufficient if all global
PMP entries fall within the range covered by the first `pmpcfg` register
(e.g., pmpcfg0). When more global entries are used, their configurations
reside in subsequent `pmpcfg` registers (pmpcfg1, pmpcfg2, etc.).
The code was only saving/restoring and checking `global_pmp_cfg[0]`,
leading to loss of configuration for entries mapped to higher `pmpcfg`
registers.
This patch fixes this by:
1. Resizing the `global_pmp_cfg` array to
`CONFIG_PMP_SLOTS / PMPCFG_STRIDE` to correctly accommodate values
from all potentially used `pmpcfg` CSRs.
2. In `z_riscv_pmp_init`, using `memcpy` to save the entire contents of
the local `pmp_cfg` array (derived from initial setup) into the
`global_pmp_cfg` array.
3. In `z_riscv_pmp_thread_init`, using `memcpy` to restore the entire
saved global configuration from `global_pmp_cfg` into a thread's
`pmp_cfg` array.
4. Updating the SMP consistency assertion in `z_riscv_pmp_init` to
compare the contents of the array element @ `index / PMPCFG_STRIDE`
of the `pmp_cfg` arrays.
These changes ensure that the configurations from all relevant `pmpcfg`
registers are preserved and correctly propagated to thread contexts.
Signed-off-by: Firas Sammoura <fsammoura@google.com>
Extend the save command to allow passing name/val pair to save a
subtree or individual setting to persistent storage.
Resolves zephyrproject-rtos#90407
Co-authored-by: Jamie <40387179+nordicjm@users.noreply.github.com>
Signed-off-by: Rami Saad <rami.saad@morgansolar.com>
psa-arch-tests includes device drivers that failed to mark
registers with 'volatile'. GCC 14.3 cleverly optimized
sequential register accesses using strd/ldrd instructions which
caused the drivers to fail.
Move the psa-arch-tests repository forward to the version which includes a
fix for this.
Signed-off-by: Keith Packard <keithp@keithp.com>
Factor out the logic for reading PMP configuration registers (pmpcfgX)
from dump_pmp_regs into a new static inline helper function,
z_riscv_pmp_read_config.
This new function encapsulates the architecture-specific (RV32/RV64)
and slot-count-specific reads of the pmpcfg CSRs, improving code
organization and potential reusability.
Signed-off-by: Firas Sammoura <fsammoura@google.com>
Apply the same CONFIG_ESPI_IT8XXX2 guard to the .h2ram_pool section
in the IT51XXX linker script, since the eSPI driver is compatible with
IT8XXX2. This keeps linker behavior consistent and avoids unused
memory allocation on non-eSPI platforms.
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
The .h2ram_pool linker section was previously always included, even on
platforms that do not enable eSPI. This caused unnecessary memory
reservation in the RAMABLE_REGION for non-eSPI configurations.
Add a CONFIG_ESPI_IT8XXX2 guard around the .h2ram_pool section definition
so that it is only included when eSPI support is enabled.
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
This is a follow-up to commit f0f5f8cdef.
There is no need to check if TXE interrupt flag is set before
calling tx_dummy_bytes(), as the function can handle the case
when it is called even though there is no room in the TX FIFO.
On the other hand, the check may be actually harmful, as it may
prevent adding more items to the TX FIFO while the SSI controller
is waiting until the FIFO achieves its transfer start level.
Remove the check then and exit the ISR loop when no dummy bytes
could be written into the TX FIFO.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Limit the loop to the smaller of nvic_iser_nb and
GPC_CPU_CTRL_CMC_IRQ_WAKEUP_MASK_COUNT to ensure safe access.
Signed-off-by: Yongxu Wang <yongxu.wang@nxp.com>
This patch just formats the file before the real patch, otherwise
the changes would be hard to read.
The only addition was a third parameter (NULL) to all the usages
of the macro WAIT_FOR, since the dangling comma triggered conflicts
between clang-format and check_compliance.py.
Signed-off-by: Marcelo Roberto Jimenez <marcelo.jimenez@gmail.com>
add adc0 to board dts
add adc to yaml test config
add adc default configuration to pinctrl
Signed-off-by: Richard Wheatley <richard.wheatley@ambiq.com>
The ssd1396 shield uses an I2C interface, and the nrf5340dk board
overlay needs a bigger buffer size by default to work.
Signed-off-by: Sebastian Viviani <sebastian.viviani@nordicsemi.no>
Cast uintptr_t to unsigned long long and adjust format specifier
accordingly to ensure compatibility on both 32-bit and 64-bit
architectures.
Signed-off-by: Tim Pambor <tim.pambor@codewrights.de>
Use %lld format specifier for variables of type eventfd_t. Cast variables
of type time_t to long long and use %lld format specifier to ensure
compatibility with 32-bit and 64-bit time_t.
Signed-off-by: Tim Pambor <tim.pambor@codewrights.de>
Use %zu format specifier for size_t type to ensure compatibility with both
32-bit and 64-bit platforms.
Signed-off-by: Tim Pambor <tim.pambor@codewrights.de>
It's triggering on things without a flash driver or flash tag...
Disable it based on the presence of a activated flash driver.
Signed-off-by: Camille BAUD <mail@massdriver.space>
Remove FIXME and re-enable autoinitiated procedures.
Removing the configuration as bug doesn't appear anymore.
Signed-off-by: Pavel Vasilyev <pavel.vasilyev@nordicsemi.no>
Add stm32f749i_disco conf file to enable input driver
for touchscreen in LVGL samples applications.
Signed-off-by: Philippe Peurichard <p.peurichard@gmail.com>
Add stm32f749i_disco conf file to support samples display driver
applications . Increase the amount of HEAP to ensure
k_malloc allocation goes well.
Signed-off-by: Philippe Peurichard <p.peurichard@gmail.com>
Extension of support of pllsai for display configuration of stm32f469
discovery board. Enable Display panel through LTDC & DSI-HOST
blocks. Enable Touch screen. Enable FMC/SDRAM for Framebuffer.
Signed-off-by: Philippe Peurichard <p.peurichard@gmail.com>
Describe mipi_dsi block available on stm32f469 & above
Allow to display data on DSI panels taking output of LTDC
after serializing data.
Signed-off-by: Philippe Peurichard <p.peurichard@gmail.com>
All nRF development kits have long traces from the SoC to the Arduino
header. Set the drive strength on the SPI ports to high to increase the
chances that the default SPI frequency defined in shields works without
errors.
This aligns the remaining DKs with the nRF91 DKs.
Signed-off-by: Jordan Yates <jordan@embeint.com>
dt_nodelabel_int_prop did not check if the property existed on the node
before accessing it, which would result in a build-time crash (and thus
build error) if used on a node which lacked the requested property.
Fix by using the common _node_int_prop() helper which handles all edge
cases properly.
Signed-off-by: Mathieu Choplain <mathieu.choplain-ext@st.com>
Button 0 and LED 0 share a GPIO pin on xgm240 boards. Remove the
`led0` alias in a board overlay to make the button sample work
out of the box.
Signed-off-by: Aksel Skauge Mellbye <aksel.mellbye@silabs.com>
Add support for xGM240-RB4316A and xGM240-RB4317A radio boards
for xGM240 modules. The two boards share pinout configuration, but
have different radio and power configurations.
Signed-off-by: Aksel Skauge Mellbye <aksel.mellbye@silabs.com>
