Add helper to handle SOF interrupts/events and new Kconfig option to
disable SOF interrupt.
Signed-off-by: Johann Fischer <johann.fischer@nordicsemi.no>
Removing stop functionality wrapped in stepper_disable since
there is a dedicated function for it.
Signed-off-by: Jilay Pandya <jilay.pandya@outlook.com>
Disabling the stepper shall not cancel any active movements.
stepper_stop() shall be used after disabling the stepper in
order to explicitly cancel stepper movements.
Signed-off-by: Jilay Pandya <jilay.pandya@outlook.com>
As per Zephyr guidelines regarding the use of inclusive language, apply
the following replacements:
- s/master/primary/g
- s/slave/secondary/g
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
Support for 8 dummy cycles in a single line RX transaction is required
for the standard JEDEC Read SFDP command. The SSI controller does not
support dummy cycles in Standard SPI mode, but the driver can simulate
those by just sending a dummy data byte.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Immediately finish an RX transfer when the RX FIFO overflow is
encountered and return the -EIO error code, which better indicates
the problem than -ETIMEDOUT that was returned previously in such
case.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
- use separate code paths for TX and RX in ISR
- make sending of dummy bytes in the single line mode (Standard
SPI) more consistent so it can be easily extended
- use value 0 instead of 0xAA for dummy bytes as there is normally
no point in making noise one the MOSI line when only receiving
data (it can only be useful in debugging transfers)
- move all writing of data in the TX FIFO to ISR to avoid broken
transfers in the single line mode (where the clock stretching
is not available) when the driver is preempted right before it
enables interrupts
- use the TX FIFO start level also for transfers without data,
so that it's not possible that the TX FIFO gets emptied between
the writes of command and address fields in the single line mode
- add a few comments to explain better how transfers are handled
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
After the START task is triggered, the clock that drives the SSI core
needs some time to become ready. Before that, writes to SSI registers
may be unsuccessful. Add a loop that performs test writes to one of
the registers after the EXMIF peripheral is resumed to ensure that it
is fully operable.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
- replace %d with %u in two error log message format strings
- add checks for maximum supported address length
- correct *_WAIT_CYCLES_MAX macros used in XIP handling routines
(although their values are valid, they belong to different SSI
registers)
- remove one unnecessary use of SPI_CTRLR0_WAIT_CYCLES_MASK
- remove doubled definitions of the XIP_CTRL register bit fields
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Clarify that commands should be run from `zephyr` folder.
Fixeszephyrproject-rtos/zephyr#90074
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
Add validation to ensure gPTP signaling messages
contain the correct TLV type, IEEE 802.1 Committee OUI
and sub-type before processing it as interval requests.
signed-off-by: Yusuke Omae <s1413091@gmail.com>
Add Kconfig to enable/disable Dynamic ED which add support for
proprietary algorithm to enhance performance in high-traffic channels.
Signed-off-by: Kapil Bhatt <kapil.bhatt@nordicsemi.no>
Added overlay for nrf9280 cpuapp iron board.
Modified overlay for nrf9280 cpuapp board to use common dtsi.
Signed-off-by: Aymen LAOUINI <aymen.laouini@nordicsemi.no>
Use signed variable for negative error codes so that potential errors
are actually detected and returned properly.
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
Add the nodes for on board EEPROM devices. Only the basic compatible
functions implemented. EUI-48 Node Address not added.
Signed-off-by: Tony Han <tony.han@microchip.com>
When the FLEXCOM is activated in the DT, configure it's register
region with strong ordered, read and write access.
Signed-off-by: Tony Han <tony.han@microchip.com>
Some tests requires to also run fsbl and load bitstream before loading
Zephyr.
Currently only --elf-file and --fsbl are suported.
But there could be also bitstream loaded via --bistream parameter but
xsdb script is missing it.
Tricky part on it is when only fsbl or bitstream are loaded they are
sharing the same argument location that's why detect if second parameter is
bitstream by matching "*.bit" in it to support all combinations.
And also switch board to jtag boot mode all the time. The reason is that
starter kits with SOM have preloaded SW already and starting in QSPI boot
mode that's why with using XSDB make sure that board is running in jtag
boot mode all the time no matter if any SW runs on it.
Signed-off-by: Appana Durga Kedareswara rao <appana.durga.kedareswara.rao@amd.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
