The mps2/an521/cpu0/ns define flash layouts in tf-m to allow
CONFIG_TFM_MCUBOOT_IMAGE_NUMBER be 1 or 2. In the Zephyr project when
building the samples the value selected is 2.
The layout changes are necessary to allow use the --max-sectors options
when signing the images. It ensures that flash layout is respected. To
allow this the compatible "soc-nv-flash" was added in the reserved
memory and the fixed-partitions were defined.
Signed-off-by: BUDKE Gerson Fernando <gerson.budke@leica-geosystems.com>
The stackprot test currently depends on compiler-generated stack frame
layouts, which can vary between toolchains and optimization levels.
This makes the overflow check fragile and may cause unintended faults.
Add a small guard buffer in alternate_thread so the intentional overflow
is always contained within the thread stack. This ensures the test
behaves consistently across toolchains, architectures, and optimization
settings.
Signed-off-by: Mohamed Moawad <moawad@synopsys.com>
build.dir-fmt format string arguments are extended. New format args are
'west_topdir' (absolute path to the west workspace directory) and
'source_dir_workspace' (relative path of the source directory to
west_topdir).
Signed-off-by: Thorsten Klein <thorsten.klein@bshg.com>
Add initial support for the AD4170-4, AD4190-4, and AD4195-4 24-bit
ADCs, including reference selection, programmable gain amplifier, ADC
conversion modes, configurable analog inputs, filter settings, and both
bipolar and unipolar operation. Supports internal and external buffered
references, and operation from a 4.75-5.25V analog supply and a
1.7-5.25V digital supply.
Signed-off-by: Kim Seer Paller <kimseer.paller@analog.com>
Document the AD4170-4, AD4190-4, and AD4195-4 low noise, high precision
24-bit ADCs, each supporting 4 differential or 8 single-ended inputs,
integrated PGA (0.5-128). All devices feature internal and external
buffered references, operate from 4.75-5.25V analog and 1.7-5.25V
digital supply.
Signed-off-by: Kim Seer Paller <kimseer.paller@analog.com>
1. There are debug info within k_sched_unlock so we shoulld add
same debug info to k_sched_lock.
2. The thread in run queue should be normal or metairq thread, we should
check it is not dummy thread.
Signed-off-by: TaiJu Wu <tjwu1217@gmail.com>
The next patch will cause mps2/an385 board fail.
The original code access 0x2000a10 but the interrupt statck
start at 0x20002000 with size 2048 byte(end at 20001800)
so the access causes stack overflow.
Increase ISR stack size to resolve this issue.
Signed-off-by: TaiJu Wu <tjwu1217@gmail.com>
Relax the `Missing a blank line after declarations` checkpatch error by
loosening the requirements for a macro to be treated as one that
declared a variable.
Currently the regex matches the pattern `DECLARE` or `DEFINE`, as long
as there are between 1 and 6 trailing `_FOO` components to the macro
name (e.g. `DECLARE_MY_TYPE()`). Zephyr however contains many macros
that don't have the trailing components but still resolve to variables
(e.g. `ATOMIC_DEFINE`, `K_MUTEX_DEFINE, etc`).
By changing `{1,6}` to `{0,6}`, we remove the requirement for the
trailing `_FOO` component(s) while still allowing them. This stops
checkpatch from erroring on patterns like this:
```
struct driver_data {
uint16_t some_value;
ATOMIC_DEFINE(some_atomic, 16);
};
```
Signed-off-by: Jordan Yates <jordan@embeint.com>
The Xilinx Zynq 7000 I2C controller has the following bugs:
- completion indication is not given to the driver at the end of
a read/receive transfer with HOLD bit set.
- Invalid read transaction are generated on the bus when HW timeout
condition occurs with HOLD bit set.
- If the delay between address register write and
control register write in cdns_i2c_mrecv function is more, the xfer size
register rolls over and controller is stuck.
As a result of the above, this patch disallows message transfers with
a repeated start condition following a read operation. Also disables
interrupts between the address register write and control register write
during message reception, to prevent transfer size register rollover.
Signed-off-by: Simon Maurer <mail@maurer.systems>
Add entries in sample.yaml for enabling h264enc / jpegenc
uvc based test on the stm32n6570_dk/stm32n657xx/sb platform.
Signed-off-by: Alain Volmat <alain.volmat@foss.st.com>
Add zephyr_h264enc and zephyr_jpegenc labels on node in order to
be able to use VENC and JPEG codec from samples.
Signed-off-by: Alain Volmat <alain.volmat@foss.st.com>
Add overlay files in order to enable usage of
the encoder in the UVC sample.
This work with platform defining node label
zephyr_jpegenc
zephyr_h264enc
Mode can be selected by using -DFILE_SUFFIX="jpegenc" or
-DFILE_SUFFIX="h264enc" when building the sample while
also adding -DCONFIG_VIDEO_ENCODER_JPEG or
-DCONFIG_VIDEO_ENCODER_H264 as well in the command line.
Signed-off-by: Alain Volmat <alain.volmat@foss.st.com>
The frame_based descriptors differ from the frame descriptors
in that there is no dwMaxVideoFrameBufferSize field.
In order to do that, add a new uvc_frame_based_discrete_descriptor
structure to be used to fill in proper information into the
frame descriptor. In addition to that, a new format descriptor
is also added for frame based transfer.
Signed-off-by: Alain Volmat <alain.volmat@foss.st.com>
This commit prepares introduction of the UVC Frame Based support by
using the struct uvc_frame_descriptor as parameter of most of the UVC
functions. struct uvc_frame_descriptor contains the common fields for
all supported frame type and then depending on the DescriptorSubtype
the pointer is casted in the correct struct definition.
Signed-off-by: Alain Volmat <alain.volmat@foss.st.com>
Add rough estimate of a worth case H264 output size.
The video_estimate_fmt_size would need more information
such as quality, profile in order to give a better
estimate for each formats so for the time being just
stick to 16bpp based size, same as for JPEG.
Signed-off-by: Alain Volmat <alain.volmat@foss.st.com>
Allow creating a pipeline as follow
camera receiver -> encoder -> uvc
If the chosen zephyr,videoenc is available, the sample will pipe
the camera receiver to the encoder and then the UVC device instead
of directly the camera receiver to the UVC.
Current implementation has several points hardcoded for the time
being:
1. intermediate pixel format between the camera receiver and encoder
is set to NV12. This shouldn't be hardcoded and should instead be
discovered as a commonly capable format from the encoder / video dev
2. it is considered that encoder device do NOT perform any resolution
change and that encoder output resolution is directly based on the
camera receiver resolution. Thanks to this, UVC exposed formats
are thus the encoder output pixel format & camera receiver
resolutions.
Signed-off-by: Alain Volmat <alain.volmat@foss.st.com>
In preparation for the introduction of video encoder support
add an indirection for handling of the buffers of the UVC
source device. Currently this is only video_dev however it
can also be an encoder device when encoder is introduced
between video capture device and the UVC device.
Signed-off-by: Alain Volmat <alain.volmat@foss.st.com>
Addition of a helper function which takes care of dequeue
from a source video device and queue into a sink video device.
Signed-off-by: Alain Volmat <alain.volmat@foss.st.com>
This updates the SHA for Xtensa HAL to latest.
This brings in the SoC configuration for intel_adsp/ace40,
and will be used with the next SDK release.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Section 4.3.7.3.6 of the I3C v1.2 specification states that a value of
0 for the max ibi size indicates an unlimited payload size. Set it to
the max it can be configured for.
Signed-off-by: Ryan McClelland <ryanmcclelland@meta.com>
Update STM32 ADC binding description now that the STM32F3 ADC asynchronous
prescaler is set through the clock property.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
Now that the ADC prescaler are set within the driver using the clock
system, remove the specific setting of the prescaler from the clock driver.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
Now that the ADC prescaler are set within the driver using the clock
system, the specific rcc compatibles for F1 and F3 are no longer useful.
Replace them with the standard one (from which they were derived).
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
Some series like F1, F3, N6 and U3 use an ADC prescaler defined in the RCC.
Instead of adding specific properties in the RCC driver, use the secondary
clock system to configure the prescaler.
The ADC driver now configures the clocks depending on their presence and
their name. Three clocks can be defined:
- the register clock (mandatory for all series)
- the kernel clock (depends on series)
- the prescaler value (depends on series)
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
To easily differentiate between the different clocks that can be configured
in device tree, make their naming mandatory, and explicit what the expected
names are.
Add these names in all dtsi and dts files that need them.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
Reworks the way the STM32_DT_CLOCK_SELECT builds its elements. Instead of
taking a mask, it takes the MSB of the field. From the MSB and LSB, we
calculate the width of the field, and this width is then stored (instead
of the mask). This allows to gain space for higher values for the fields.
This larger space is necessary to add the selection of the ADC prescaler
on STM32N6 because it is an 8-bit long field.
The allowed width is from 1 to 8 (and internally stored as 0-7 to fit on
3 bits).
STM32_DT_CLKSEL_MASK_GET keeps the same name, since we still need the mask,
and returns the bitmask from the width with the BIT_MASK macro. Other
STM32_DT_CLKSEL_MASK_* macros are renamed with WIDTH.
All call to STM32_DT_CLOCK_SELECT are updated to reflect the change and use
a width instead of a mask.
This also fixes a few issues like STM32H7 MCO macros, and adds MCO_PRE for
STM32N6.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
- Increase the size of the storage partition to 2 sectors
because a single sector makes it unusable as reported
by test_flash_copy.
This change will breaks backward compatibility regarding
MCUboot firmware update support.
Add a migration guide note about changes to the flash layout
and warn users about potential firmware upgrade failures.
Signed-off-by: Fabrice DJIATSA <fabrice.djiatsa-ext@st.com>
update CONFIG_TEST_DRIVER_FLASH_SIZE to match actual flash size.
The test was previously failing due to a mismatch between the expected
flash size (827392 bytes) and the actual size reported by flash_get_size()
(1048576 bytes).
This update sets CONFIG_TEST_DRIVER_FLASH_SIZE to 1048576 to reflect the
correct size of the flash device as defined in the reference manual for
the NUCLEO_WB55RG board.
The increase in required flash size (216K) for the full stack M0 binary
also justifies aligning the test configuration with the actual hardware
capabilities.
This change ensures the test passes and accurately reflects the flash
memory layout.
Signed-off-by: Fabrice DJIATSA <fabrice.djiatsa-ext@st.com>
Support I2C target error callback in I2C driver when
registered by the bus target consumer.
Signed-off-by: Khaoula Bidani <khaoula.bidani-ext@st.com>
Signed-off-by: Julien Racki <julien.racki-ext@st.com>
Add a 1 second delay before printing environment variables to give the
shell time to initialize and print its prompt. This prevents a race
condition where the shell prompt could interleave with the environment
variable output on SMP systems, causing test failures.
Without this delay, the output could appear as:
BUILD_VERSIuart:~$ ON=v4.2.0...
With the delay, the shell completes initialization first:
uart:~$
BOARD=...
BUILD_VERSION=...
ALERT=
This fixes the sample.posix.env test timeout on FVP v9a/smp where the
test harness regex failed to match the corrupted output.
Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
use CONFIG_RISCV_ISA_EXT_F to set CONFIG_CPU_HAS_FPU.
Same for CONFIG_RISCV_ISA_EXT_D and
CONFIG_CPU_HAS_FPU_DOUBLE_PRECISION.
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
