stm32 mipi dsi driver requires a reset control hence ensure that
CONFIG_RESET is properly selected to allow proper build.
Signed-off-by: Alain Volmat <alain.volmat@foss.st.com>
stm32 dcmi driver requires a reset control hence ensure that
CONFIG_RESET is properly selected to allow proper build.
Signed-off-by: Alain Volmat <alain.volmat@foss.st.com>
stm32 dcmipp driver requires a reset control and pinctrl
(depending on the configuration) hence ensure that
CONFIG_RESET and CONFIG_PINCTRL are properly selected to allow
proper build.
Signed-off-by: Alain Volmat <alain.volmat@foss.st.com>
Ensure NSBank values are validated at build time.
That helps to identify and fix incorrect bank values.
Signed-off-by: Georgij Černyšiov <geo.cgv@gmail.com>
Simplifies the driver code:
* Use existing FMC_NORSRAM_DEVICE and FMC_NORSRAM_EXTENDED_DEVICE
defines. No need to keep references to them in the driver's config.
* Refine initialization loop.
Signed-off-by: Georgij Černyšiov <geo.cgv@gmail.com>
Add support for the SDMMC clock bypass feature for those SoCs that have
it. This provides a SDMMC bus speed double that of `clk-div = <0>`.
Updated the `clk-div` documentation at the same time to be clearer on
how the bus clock speed is determined.
Signed-off-by: Jordan Yates <jordan@embeint.com>
Explicitly initialise the SDMMC initialisation struct to make it clear
the configuration being applied.
Signed-off-by: Jordan Yates <jordan@embeint.com>
A public API call that sends ACL data — for example, `bt_gatt_notify` —
can be invoked from a preemptive thread context. This API, in turn,
calls the `raise_data_ready` function, which adds an L2CAP channel to
the `l2cap_data_ready` list.
The atomic variable used to create a critical section around
`l2cap_data_ready` did not work, because a preemptive thread can be
pre-empted at any time. This means that regardless of the `atomic_set`
result, we cannot trust it — the thread could be preempted after the
call, and the atomic variable state could be changed (specifically by
the TX processor in this case). The same issue applies to
`bt_conn_data_ready`, which is called next.
When making an L2CAP channel ready for sending data, we need to use a
critical section when appending a channel to the `l2cap_data_ready`
list. The same applies to the `conn_ready` list.
Since cooperative threads can only be rescheduled explicitly, we must
ensure there are no rescheduling points when accessing either the
`l2cap_data_ready` or `conn_ready` lists.
For `l2cap_data_ready`, this occurs in `get_ready_chan`, which is called
from `l2cap_data_pull`, which in turn is called by the TX processor. For
`conn_ready`, it occurs in `get_conn_ready`, which is also called from
the TX processor. Both functions have no rescheduling points when
working with their respective lists, so they do not require a critical
section.
This change removes the atomic variables previously used to create a
critical section for both lists, as they were ineffective. Instead,
`k_sched_lock`/`k_sched_unlock` are used where code may be executed from
a preemptive thread context. The `sys_slist_find` function is used to
check whether a channel or connection is already in the corresponding
list.
Fixes#89705
Signed-off-by: Pavel Vasilyev <pavel.vasilyev@nordicsemi.no>
Add CONFIG_OPENTHREAD_ROUTER_SELECTION_JITTER_OVERRIDE
Kconfig option that enables setting the router selection
jitter to CONFIG_OPENTHREAD_ROUTER_SELECTION_JITTER at
startup.
Signed-off-by: Damian Krolik <damian.krolik@nordicsemi.no>
STM32G0x SoCs reference manuals say that for Shutdown mode (STM32G0x1)
or Standby mode (STM32G0x0) entry (used for Power OFF entry), that
"WUFx bits are cleared in Power status register 1 (PWR_SR1)".
Therefore call LL_PWR_ClearFlag_WU() unconditionally (regarding
CONFIG_STM32_WKUP_PINS) in z_sys_poweroff() sequence.
Reference manuals references:
- STM32G0x0: RM0454 Rev 5, Table 25.
- STM32G0x1: RM0444 Rev 6, Table 34.
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
STM32F4x SoCs reference manuals say that for Standby mode (aka Power OFF)
entry, "WUF bit is cleared in Power Control register (PWR_CR)" [1]
and "WUF bit is cleared in Power Control/Status register (PWR_CR)" [2].
Therefore call LL_PWR_ClearFlag_WU() unconditionally (regarding
CONFIG_STM32_WKUP_PINS) in z_sys_poweroff() sequence.
Reference manuals references:
- [1] STM32F401xx: RM0368 Rev 6, Table 20.
- [2] STM32F469xx/STM32F479xx: RM0386 Rev 6, Table 23.
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
STM32C0x SoCs reference manual says the wakeup source status flags (from
register PWR_SR1) are not cleared by hardware and therefore should be
cleared by software before entering Standby or Shutdown power mode.
Therefore call LL_PWR_ClearFlag_WU() unconditionally (regarding
CONFIG_STM32_WKUP_PINS) in z_sys_poweroff() sequence.
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Fix STM32G0x0 SoCs power off sequence that do not support Shutdown mode
and which deppest power mode state is Standby mode.
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
This commit updates I2C_DMA_DATA_INIT() macro to use
IF_ENABLED(DT_INST_DMAS_HAS_NAME(...), (...)),
so that the DMA configuration field is only generated if the
corresponding DMA property exists in the Device Tree.
This prevents macro expansion errors and allows a mix of I2C
peripherals with and without DMA support in the same build.
Signed-off-by: Khaoula Bidani <khaoula.bidani-ext@st.com>
Remove CONFIG_SOC_SERIES_NSIM_ARC_V_RMX conditional check from
zephyr_compile_options_ifdef and apply all extensions
unconditionally when using arcmwdt compiler.
Since this CMakeLists.txt is already SoC-specific, the
additional config check is redundant.
Signed-off-by: Afonso Oliveira <afonsoo@synopsys.com>
Update the hardware configuration for the Synopsys nSIM ARC-V RMX100:
- Change CLINT base address from 0x2000000 to 0xa0010000. The CLINT
is now created by default in the RMX100 configuration, with its
MMIO base already configured to use this address.
- Update nSIM MMIO base address to 2560 to align with the new memory
map requirements.
- Remove PLIC support as the ARC-V RMX architecture only supports
APLIC (Advanced Platform-Level Interrupt Controller), not PLIC.
Note that APLIC support is not yet available in Zephyr, so
interrupt controller functionality will be limited until APLIC
is implemented.
- Replace legacy MPU configuration with PMP (Physical Memory Protection):
Remove mpu_version, mpu_regions, and mpu_granule properties and add
ARCV_PMP interface with 16 regions and granule=1. The MPU options
were legacy and PMP is the standard RISC-V memory protection mechanism.
These changes align with the latest ARC-V RMX100 hardware memory map
and architectural requirements.
Signed-off-by: Afonso Oliveira <afonsoo@synopsys.com>
Rename SOC configuration symbols from generic names to more specific
ones that include the vendor and platform information. This improves
clarity and prevents potential naming conflicts.
Changes:
- SOC_SERIES_RMX -> SOC_SERIES_NSIM_ARC_V_RMX
- SOC_RMX100 -> SOC_NSIM_ARC_V_RMX100
Signed-off-by: Afonso Oliveira <afonsoo@synopsys.com>
Add the pyocd as runner for the stm32h7s3l8 nucleo or stm32h7s78 dk
so that debugging becomes possible if openocd is not available.
Check with 'pyocd list --target'
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Define SAI1 node for STM32H7xx series.
Add STM32H7xx related DMA configs.
Enable samples/drivers/i2s/output for nucleo_h745zi_q/m7
Signed-off-by: Mario Paja <mariopaja@hotmail.com>
Add external interrupt support for Renesas RZ/A3UL, V2L
Signed-off-by: Quang Le <quang.le.eb@bp.renesas.com>
Signed-off-by: Tien Nguyen <tien.nguyen.zg@renesas.com>
Document the S32DS and S32Debug Probe OS supported version,
and guide to upgrade the OS of the S32DebugProbe.
Signed-off-by: Ha Duong Quang <ha.duongquang@nxp.com>
S32DS3.6 requires to use python 3.10, so update
PYTHONPATH for S32DS3.6 when debug on windows.
Update to verify new behavior of supported commands
with S32D3.6 on windows.
Update to find out the usb device connected by VID
and PID instead of class "NXP Probes" on windows
Because based on the S32 Debug probe OS version the
device class of USB is changed. Therefore a reliable
way to identify the probe is check the USB VID and PID.
Signed-off-by: Ha Duong Quang <ha.duongquang@nxp.com>
When a reset coccurs the sram1 where the m_state value is stored
is erased. Then the board indefinitely reboots.
Avoid this excluding the target board.
Or set the SRAM13_RST bit in the option byte in FLASH_OPTSR2_CUR.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Added helper Kcoinfig option USE_ISR_WRAPPER which can be used to
include isr_wrapper even if GEN_SW_ISR_TABLE is not enabled. This
is needed to enable configurations where only IRQ vector table is
used with multithreading (only direct isr used). This change is
backward compatibible with previous config.
Signed-off-by: Łukasz Stępnicki <lukasz.stepnicki@nordicsemi.no>
External flash memory is typically not used, so it should
be disabled by default. The GPIO6 port used by this device
should also be disabled.
Signed-off-by: Adam Kondraciuk <adam.kondraciuk@nordicsemi.no>
Remove the reference to TrustZone for the stm32h7s3 nucleo and
the stm32h7s7 disco. They do not have the feature embedded.
Other fixes about non-applicable features.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Added support for the Adafruit Feather RP2040, based on existing board
definitions for the Qt Py RP2040 and others.
Board image (c) Kattni Rembor, CC-BY-SA-3.0 per licensing info at
https://learn.adafruit.com/assets/100345.
Signed-off-by: Anson Mansfield <amansfield@mantaro.com>
The previous 1ms sleep introduced unnecessary latency
while waiting for the SUSPF flag.
Switching to a 750µs busy-wait provides a more responsive
and precise delay,improving performance in time-sensitive contexts.
Signed-off-by: Fabrice DJIATSA <fabrice.djiatsa-ext@st.com>
If st_stm32_fmc_sdram compatible is present, get base address and
external memory size. Add stm32f469i-disco overlay file
Signed-off-by: Philippe Peurichard <p.peurichard@gmail.com>
On stm32f469i-disco board, a 16MBytes SDRAM external memory
is connected via FMC to STM32F4 SoC.
Signed-off-by: Philippe Peurichard <p.peurichard@gmail.com>
In current implementation, the attribute of the registered SDP record
will not be included in responding packet if the attribute data length
is more than the MAX payload size(`MIN(SDP_MTU, sad->sdp->chan.tx.mtu)
- sizeof(struct bt_sdp_hdr)`). And it causes the failure of ssa or sa
discovery.
Improve the SDP server to support the case by extending the
continuation state length. A 4 bytes space is extended to store the
attribute offset.
In this way, the attribute can be transmitted in segments according
to the reaming space of the responding buffer.
Signed-off-by: Lyle Zhu <lyle.zhu@nxp.com>
Clear the suspended status and submit the resume event once the remote
wakeup signaling is finished. Clear the suspended status on bus reset as
well.
Signed-off-by: Johann Fischer <johann.fischer@nordicsemi.no>
