Added overlay for nrf9280 cpuapp iron board.
Modified overlay for nrf9280 cpuapp board to use common dtsi.
Signed-off-by: Aymen LAOUINI <aymen.laouini@nordicsemi.no>
Use signed variable for negative error codes so that potential errors
are actually detected and returned properly.
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
Add the nodes for on board EEPROM devices. Only the basic compatible
functions implemented. EUI-48 Node Address not added.
Signed-off-by: Tony Han <tony.han@microchip.com>
When the FLEXCOM is activated in the DT, configure it's register
region with strong ordered, read and write access.
Signed-off-by: Tony Han <tony.han@microchip.com>
Some tests requires to also run fsbl and load bitstream before loading
Zephyr.
Currently only --elf-file and --fsbl are suported.
But there could be also bitstream loaded via --bistream parameter but
xsdb script is missing it.
Tricky part on it is when only fsbl or bitstream are loaded they are
sharing the same argument location that's why detect if second parameter is
bitstream by matching "*.bit" in it to support all combinations.
And also switch board to jtag boot mode all the time. The reason is that
starter kits with SOM have preloaded SW already and starting in QSPI boot
mode that's why with using XSDB make sure that board is running in jtag
boot mode all the time no matter if any SW runs on it.
Signed-off-by: Appana Durga Kedareswara rao <appana.durga.kedareswara.rao@amd.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
If supported, the data and control source for a signal can come from
either software or hardware. This change adds a custom configuration
flag to set this for a specific pin.
Signed-off-by: Corey Wharton <xodus7@cwharton.com>
Remove redundant register updates in pinctrl_configure_pins, and replace
the improper (and inefficient) use of bitwise OR assignment (|=) with
direct assignments when writing to the write-only BSHR registers
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
Create and select the proper module device tree file which loads the
correct radio config for the MGM240P module.
Signed-off-by: Tamas Jozsi <tamas.jozsi@silabs.com>
Add device tree and support files for the Nano Matter board
based on the Silicon Labs MGM240SD22VNA chip.
Signed-off-by: Tamas Jozsi <tamas.jozsi@silabs.com>
Enable connecting native sim to a physical board running hci_uart
without usage of Bumble or other intermediary steps, but rather using
common h4 hardware driver.
Most commonly used port is USB CDC-ACM, as by default for most nRF
boards.
Signed-off-by: Dmitrii Sharshakov <d3dx12.xx@gmail.com>
In some cases UART drivers might have too high init priorities
so HCI must be initialized even later if used with those.
One example is zephyr,native-tty-uart.
Signed-off-by: Dmitrii Sharshakov <d3dx12.xx@gmail.com>
Ensure that the various configuration and conversion tables are marked
as const to save on RAM usage.
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
Align code with the comment :) There apparently was a copy-paste issue
from the clock_control_on code.
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
Include rpi_pico.overlay from the rpi_pico_rp2040_w.overlay in order to
have `pico/rp2040/w` board to work out of the box.
Signed-off-by: John Lin <john.lin@beechwoods.com>
Prevent out-of-bounds access in nxp_pint_pin_enable by fixing the
comparison to use >= instead of >.
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
This enables the clock_control driver build on bl60x.
It is currently deferred init, due to being incompatible
with current SDK-based boot, to avoid later giant PR.
Signed-off-by: Camille BAUD <mail@massdriver.space>
The current CMakeLists.txt uses hardcoded flash addresses for the
bootloader and application, which may not match the slot defined
in the DTS file. This can lead to inconsistencies when flashing
and running images.
This update introduces support for using CONFIG_FLASH_LOAD_OFFSET
and applies CONFIG_BUILD_OUTPUT_ADJUST_LMA if specified,
ensuring that the final image address aligns with the DTS
and runtime expectations.
Note: For ESP32-C6, a custom workaround is included since the
LPCORE does not support MCUboot images.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Updated buffer length variables to be size_t as they need to be able to
represent the maximum buffer size which is 4092.
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
Add several more luma-only formats also known as grayscale, of variable
bit depth, 0-padded to fit 16-bits per pixel: Y10, Y12, Y14, Y16
Signed-off-by: Josuah Demangeon <me@josuah.net>
This is an X86 specific option and should not appear as generic debug
option.
Fixeszephyrproject-rtos/zephyr#52929
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Introduce an index field to the video buffer structure to help track
individual buffers throughout the workflow.
This is particularly useful in scenarios where buffers are wrapped
in a pool, such as in GStreamer. The index allows efficient
identification of the currently dequeued buffer without needing to
iterate through the entire pool and compare buffer addresses.
Signed-off-by: Phi Bang Nguyen <phibang.nguyen@nxp.com>
Document the change of semantics of video_format.pitch field,
modified in commit 33dcbe37cfd3593e8c6e9cfd218dd31fdd533598.
Signed-off-by: Josuah Demangeon <me@josuah.net>
In case of the st,stm32-ospi-nor compatible
new property and node definitions will requires new macro
to get the external NOR flash base address and size
Signed-off-by: Francois Ramu <francois.ramu@st.com>
This change defines the "st,stm32-ospi-nor" compatible Node
in conformance to the DTS specifications
Includes the size property (in Bits) of the external memory device
Signed-off-by: Francois Ramu <francois.ramu@st.com>
New property of the st,stm32-ospi-nor compatible gives
the external NOR flash in bits.
The property of the st,stm32-ospi compatible gives
the external NOR flash base address
Signed-off-by: Francois Ramu <francois.ramu@st.com>
The st,stm32-ospi compatible is defining the reg property
with the register address and size at first index
followed by the external mem base address and max allocated size.
For the stm32H7, stm32L4plus, stm32L5, stm32U5 series.
ospi1 is addressing max 256 MBytes from 0x90000000
ospi2 is addressing max 256 MBytes from 0x70000000
Signed-off-by: Francois Ramu <francois.ramu@st.com>
