Add PCI device IDs for common Intel Raptor Lake variants and Alder Lake N.
These all have cAVS2.5 audio DSP.
Signed-off-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
Numerically sort the PCI DIDs for cAVS2.5 hardware. This follows
the convention in e.g. Linux and coreboot and eases maintainance. No
functional change.
Signed-off-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
The "Detected cAVS 1.8+ hardware" message is misleading as it implies
some version of Intel cAVS hardware has been found, while in fact this
script supports also other types of hardware, including Intel ACE.
Signed-off-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
Clean up code documentation to drop references to platforms no longer
supported in the code. Continues the cleanup started in commit
086e4f84ed ("intel_adsp: cavstool: Remove
legacy code").
Signed-off-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
Added a check in unicast_client_ase_discover_cb that if
no ASE was discovered, then it would stop the discovery
there instead of attempting to call
unicast_client_ase_cp_discover to discover the control point
which would not be useful to use anyhow.
This terminates the discovery earlier in case of the remote
side not supporting the audio direction we are discovering.
Signed-off-by: Emil Gydesen <emil.gydesen@nordicsemi.no>
The default configuration for PINCTRL should not be set with
the other default configurations in .defconfig, instead select
a default value as part of defining the UART driver.
Signed-off-by: Andrew Davis <afd@ti.com>
Add initial SoC support for the TI J721E SoC series Cortex-R5 core.
TRM for J721e https://www.ti.com/lit/zip/spruil1
File: spruil1c.pdf
Signed-off-by: Prashanth S <slpp95prashanth@yahoo.com>
Signed-off-by: Andrew Davis <afd@ti.com>
Use full board name in cmake file.
Akin to the fix done in zephyrproject-rtos#80270
zephyrproject-rtos#80270
following the changes from
zephyrproject-rtos#77250
In which twister now uses the full board name when calling cmake.
Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
In case the host doesn't pull the new data from the endpoint, the work task
would schedule itself again delayed (at the max. priority). When there is
no terminal program or active application reading the endpoint this
results in a constant polling of the endpoint burning up to 5% of the
CPU cycles.
By using a atomic flag for tx busy, the polling is solved and changed into
a postponed execution of the next work task which saves up to 5% of
CPU cycles and allows a better real-time behavior for other tasks.
Secondly, if the TX interrupt is disabled but there is still data in the TX
FIFO (ring buffer), the implementation will continue to trigger subsequent
TX work and attempt to flush the data to the host.
Signed-off-by: Vincent van der Locht <vincent@synchronicit.nl>
DT_INST* should be used in MSPI_CONFIG or device tree value capture
will fail sliently and fall back to defaults.
Signed-off-by: Swift Tian <swift.tian@ambiq.com>
Switch from using direct `strtol` calls to `shell_strtol`.
This change leverages the extensive error handling provided
by `shell_strtol`.
Signed-off-by: Pisit Sawangvonganan <pisit@ndrsolution.com>
Since `<host>` is a mandatory argument, the (_mand, _opt) values
should be adjusted to 2 and 12, respectively.
Note that `_mand` includes the number of mandatory arguments,
including the command name (`ping` itself).
Signed-off-by: Pisit Sawangvonganan <pisit@ndrsolution.com>
This commit does the following:
1. tests set_callback and user_data
2. fixes the api as well as the drivers by passing user_data
back to the set callback
Signed-off-by: Jilay Pandya <jilay.pandya@outlook.com>
IS25LP flash chips have a similar P[6:3] register to the IS25WP series,
and need the same workaround.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
IS25WP flash chips support 133MHz only when P[6:3] is programmed, which
will not occur during the SFDP probe sequence used in the FlexSPI nor
driver. With the default P[6:3] value, the best frequency supported for
read instruction 0xEB is 104MHz, so set this for all boards using this
flash chip with the FlexSPI nor driver.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Some NXP boards program the read parameters bits (P[6:3]) within the
IS25WP flash device during init, which will result in JESD216 probe
commands failing (as the number of dummy cycles will be incorrect). Add
handling to force these volatile bits to their default value to the
flexspi flash driver.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Quad enable method 5 reads status register 2 (one byte), but then writes
to 2 bytes to the status registers, so we need to shift the output
buffer in order to manage this correctly.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Writing the quad enable bit on flash chips typically requires a write
enable instruction be issued before writing the non-volatile status
register, and the flash may remain busy briefly after programming this
bit. Add code to send the WREN instruction, and to wait for the flash to
finish programming after writing the status register.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Move the LUT used for probing to be stored in .data, instead of on the
stack. This reduces stack usage during probe by 192 bytes, which avoids
stack overflows that were occurring on some platforms.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Even in cases where the alt-addr is set, we can still use the INT pin
during probe. Some boards require this, as if a reset GPIO is not
defined the INT pin may still need to be toggled in order to initialize
the GT911 IC correctly.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
This commit updates the CI workflows to use the CI image v0.27.3, which
includes Zephyr SDK 0.17.0.
Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
This commit increases the test timeout for the wait queue benchmark tests
to 120 seconds because these tests frequently hit the default timeout of 60
seconds during execution.
Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
We now use hwmv2 to list boards instead of relying on twister specific
config files.
One yaml files (twister.yaml for now) will have all the data needed for
all possible targets and variations of a board reusing most of the data
where possible and variations can override the top level data.
Twister keeps track of 'aliases' of boards and identifies that for
example native_sim is the same as native_sim/native, so either names
will be possible in both test yaml files or on the command line,
however, the reporting will always use the full name, so no there is no
confusion about what is being tested/built.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
- Following similar approach followed on spi_mcux_lpspi driver.
- Enabling DMA by default when SPI RTIO is selected to favor
non-blocking transfers.
Signed-off-by: Luis Ubieda <luisf@croxel.com>
Updated ADXL372 driver with RTIO stream functionality.
RTIO stream is using both FIFO threshold and FIFO full triggers.
Together with RTIO stream, RTIO async read is also implemented.
Signed-off-by: Vladislav Pejic <vladislav.pejic@orioninc.com>
Enable support for FRDM_RW612 with memc driver sample, using attached
aps6404l PSRAM.
Signed-off-by: David Missael Maciel <davidmissael.maciel@nxp.com>
Some instances of the FLEXSPI IP permit limiting AHB bus access so that
no memory access requests will straddle a page boundary. Add a property
to manage this setting.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
is66wvq8m4 PSRAM always requires the address to be left shifted by
5 bits, regardless of which FLEXSPI port it is on. Fix the addressShift
assignment to be unconditional
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
The ADDRSHIFT bit simply left shifts the address written to IPCR0[SFAR],
(or the address used for AHB access), by 5 bits before sending it to the
attached memory. This bit does not have an effect on the base address
used to access the flash/psram device.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Transactions should result in a single transfer call not multiple
transfer calls. Transceive isn't supported by i2c and so the TXRX op
isn't validated for success anymore.
Signed-off-by: Tom Burdick <thomas.burdick@intel.com>
