STM32L4 devices, except STM32L412 STM32L422 STM32L4P5 STM32L4Q5, have
32 4-byte battery-backed RTC backup registers. Other STM32L4 devices
have backup registers in tamper module, not used in Zephyr.
Signed-off-by: Patryk Duda <pdk@semihalf.com>
All STM32L1 devices have 4-byte battery-backed RTC registers, but
they have different number of registers:
STM32L151Xb-a has 5 registers.
STM32L151Xb has 20 registers.
STM32L151Xc, STM32L152Xc, STM32L152Xe have 32 registers.
Signed-off-by: Patryk Duda <pdk@semihalf.com>
Add BBRAM entry for all STM32H7 microcontrollers except STM32H7A3 and
STM32H7B3 which have backup registers in tamper module.
Signed-off-by: Patryk Duda <pdk@semihalf.com>
All supported STM32F3 devices have 4-byte battery-backed RTC registers,
but they have different number of registers:
STM32F303x8 and STM32F334 have 5 registers.
STM32F303xc and STM32F303xe have 16 registers.
STM32F302x8 has 20 registers.
STM32F373 has 32 registers.
Signed-off-by: Patryk Duda <pdk@semihalf.com>
Among supported devices only STM32F031, STM32F051, STM32F072 and
STM32f09x have 5 4-byte battery-backed RTC registers.
Signed-off-by: Patryk Duda <pdk@semihalf.com>
STM32 battery-backed RAM is organized in 4 byte registers. Number of
registers can vary between models from 5 to 32 registers.
Usually, the registers are part of RTC. On some variants they are part
of tamper module. On STM32F1 the registers are in separate module. For
now, only backup registers from RTC are supported.
Signed-off-by: Patryk Duda <pdk@semihalf.com>
`spi_is_ready` function is being deprecated in favor of
`spi_is_ready_dt` so let's replace the old usage in the tree.
Signed-off-by: Bartosz Bilas <bartosz.bilas@hotmail.com>
Add `spi_is_ready_dt` function that validates SPI DT spec
is ready and it allows the user to pass `spi_dt_spec` directly.
Signed-off-by: Bartosz Bilas <bartosz.bilas@hotmail.com>
Add definitions for DMAs, Digital Audio Interfaces (DAIs) and
the necessary clocks to enable full use of audio peripherals
in the intel_adsp_cavs25_tgph boards.
Link: https://github.com/thesofproject/sof/issues/6710
Signed-off-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
STM32 counter driver uses switch statement in which cases don't end
with break or return intentionally.
Affected switches in counter driver check status of all timer channels
(maximum 4 channels), but the number of channels is not determined
during compilation. In switch, we jump to channel with highest number
and then check other channels with lower numbers.
Compiler can warn about it, so this patch adds information that it was
intentional.
Signed-off-by: Patryk Duda <pdk@semihalf.com>
Add configuration for built-in display.
LCD has a Sitronix ST7735S controller that is connected to the SPI bus.
Using it with the ST7735R driver.
Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@gmail.com>
Clarify:
- Board directory name does not need to match board name
- Give example of multi board directory
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
Fixes an issue with large packets being received, these packets are
chunked into 127-byte frames for the serial transport but this system
is not needed for the dummy transport as it has a fixed size buffer.
Signed-off-by: Jamie McCrae <jamie.mccrae@nordicsemi.no>
The device information handler can be used to retrieve information about
the configuration of the configured device such as board name, board
revision, firmware version and build date.
Signed-off-by: Jamie McCrae <jamie.mccrae@nordicsemi.no>
This PR clarifies the violation messages emitted by gitlint when
checking the commit message. For example:
* Before: `43: UC4 Line exceeds max length (N>75): "..."`
* After: `43: UC4 Commit line exceeds max length (N>75): "..."`
This makes it easier to identify the source of the error since there is
currently no additional context besides the error code UC*. I recently
pushed a commit that had some sample code as part of the commit body
that exceeded the lenght limit, and thought the error was referring to
one of my source files based on the line it showed. (feel free to laugh
at me, but let's make it better for the next person)
Signed-off-by: Tristan Honscheid <honscheid@google.com>
The FAT driver converts zephyr paths like /SD:/foo into ELM-FATFS paths
like SD:/foo. Document this behaviour by extracting it into a separate
function (and adding a sanity check).
Signed-off-by: Armin Brauns <armin.brauns@embedded-solutions.at>
Do not assert on invalid PDU in CIS create procedure. Instead terminate
with reason BT_HCI_ERR_LMP_PDU_NOT_ALLOWED
Signed-off-by: Erik Brockhoff <erbr@oticon.com>
Adds a missing menuconfig for the DSP library as well as fix an issue
with the zephyr library being a STATIC library and having no sources
in the case of the cmsis backend.
Signed-off-by: Yuval Peress <peress@google.com>
Cortex M0 support was previously disabled due to a compiler bug.
SDK 15.1 includes GCC 12.1 which solves this issue.
Fixes: #52788
Signed-off-by: Jon Escombe <jone@dresco.co.uk>
This commit properly writes back cached read pointer in spsc buffer
when freeing the memory.
Signed-off-by: Radoslaw Koppel <radoslaw.koppel@nordicsemi.no>
This feature is not used in most tests, as there is no logic in C code that
utilizes `#ifdef TEST_x` statement.
The only test that does that is `tests/subsys/settings/fcb/` where `#ifdef
TEST_LONG` is used, so leave that test case untouched.
Signed-off-by: Marcin Niestroj <m.niestroj@emb.dev>
-- Corrected PDU time stamps to match expected reference anchor point
-- Corrected failing test_rx_unframed_dbl_split according to expected
time stamps.
Signed-off-by: Nirosharn Amarasinghe <niag@demant.com>
Corrected an omission in the ISO-AL that required an SDU interval to
be added to the reconstructed RX time stamps for each SDU after the
first.
Signed-off-by: Nirosharn Amarasinghe <niag@demant.com>
NXP LPUART IP supports rs485 mode when transceiver driver enable
using RTS. Allow setting rs485 mode up via the "nxp,rs485-mode"
dts property. "nxp,rs485-de-active-low" dts property can be used
for set RTS polarity.
Signed-off-by: Grixa Yrev <GrixaYrev@yandex.ru>
Adds support for the Adafruit ItsyBitsy nRF52840 Express.
This board ships with the UF2 bootloader, so the device has
been set up so that Zephyr applications are flashed the
same way that other (Adafruit) firmware is flashed with the
UF2 bootloader.
This has been tested locally, and the button, blinky and
led_apa102 samples run without problems.
Signed-off-by: Embla Flatlandsmo <embla.flatlandsmo@gmail.com>
The different boards with stm32 which have node enabled in their DTS
also requires the HSI48 clock to be enabled.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
The different boards with stm32 which have node enabled in their DTS
also requires the HSI48 clock to be enabled.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
The different boards with stm32 which have node enabled in their DTS
also requires the HSI48 clock to be enabled.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
The nucleo_wb55rg platform has Bluetooth feature that
requires the HSI48.
The board DTS enables the HSI48MHz clock for that purpose.
And also selects it as the source (default) of the CLK48.
Note that the clk48 node must be enabled for any another source.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Add the HSI48 clock to the stm32 devices that have this
clock signal.
Within a stm32 family, only few might have the
RCC_HSI48_SUPPORT.
STM32WB has a CLK48 mux.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
The stm32 devices which have a HSI48 clock possibility.
for stm32F0, stm32G0, stm32G4, stm32H7, stm32L0,
stm32L4, stm32L5, stm32U5, stm32WB
Signed-off-by: Francois Ramu <francois.ramu@st.com>
The HSI48 is enabled by clock control driver.
It is no more done by each driver that requires this clock
However when using rng or sdmmc or bluetooth/ipm or usb,
the HSI48 clock must be present in the DTS.
Add a warning for this particular check but keep the deprecated
HSI48 clock enable : keeping for legacy but to remove later.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
For the stm32 devices that have a HSI48 clock,
the driver enables it, like any other fixed clock,
if needed and supported by the serie.
For stm32L0, SYSCFG VREFINT is also required.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
