Update thermometer sample with mcp970x temperature sensor.
Removing test with frdm_k64f integration platform as it doesn't
provide an ambient temperature sensor.
Removing the bbc_microbit board as it only seems to provide the
die temperature of the nRF51 SoC and not an ambient temperature
sensor.
Signed-off-by: Nick Ward <nix.ward@gmail.com>
Use recently introduced GENMASK64() macro. Although it does not make
difference for the target platform, it makes code clearer.
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
NVMe disks are supported, let's provide some documentation about the
driver and how to enable it.
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
On Qemu x86_64 it is possible to emulate an NVMe controller and disk on
the PCIe bus, so let's add this case here to verify how the newly added
NVMe controller and disk driver perform, relatively to the host.
This will prove to be useful to evaluate the optimization to be made, or
the possible regression that could happen on future changes.
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
On Qemu x86_64 it is possible to emulate an NVMe controller and disk on
the PCIe bus, so let's add this case here to verify that the newly added
NVMe controller and disk driver works fine.
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
As it is meant to be used on the tests/drivers/disk test case, it will
currently create a dummy 1Mb image on a fixed path to serve as a NVMe
disk.
It could be made of an alternate path and size, if necessary.
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
This is currently the only end-point where multiple threads can access
the NVMe device (all calls are synchronous).
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
Pre-allocating PRP list for such purpose. Which PRP list is relevantly
filled in depending on the data size and data pointer page alignment.
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
Based on FreeBSD's implementation made by James Harris, Intel Copyright
2012-2016.
Namespace in this context, will be a disk. It's not exposed from DTS, as
an actualy NVMe hardware controller card can bring more than one
namespace (disk).
Thus namespace are not instanciated through the device driver model, but
statically allocated and runtime configured, depending on what the
controller exposes.
By default the amount of namespace supported is one as it is the most
common setup.
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
Based on FreeBSD's implementation made by James Harris, Intel Copyright
2012-2016.
This is the corner stone of the whole NVMe logic: sending commands and
getting replies, all through memory shared from the host to the
controller.
Then using it to inialize admit/IO queues and identifying the
controller.
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
Based on FreeBSD's implementation made by James Harris, Intel Copyright
2012-2016.
Since Zephyr does not propose any advanced interfaces as FreeBSD (bus
abstractions, memory and DMA abstraction and many more), this comes with
a much simplified and Zephyr-ish way to instanciate, initialize and use
NVMe controller.
ToDo: IO Queues cannot be more than 1. Macros will need to be improved to
manage the case of 2+ IO queues.
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
Under disk bindings. NVMe is a purely PCIe based technology, thus the
relevant includes.
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
There is no event reporting WiFi disconnect, create a polling
work for this and report the event.
Signed-off-by: Loic Poulain <loic.poulain@linaro.org>
It has been observed that sockets can be in bad state after
boot. Be sure to correctly reset local port and any 'server'
mode before configuring client mode.
Signed-off-by: Loic Poulain <loic.poulain@linaro.org>
- We should wait indefinitely if msecs is -1 (FOREVER).
- We can directly return if data is already available in FIFO.
Signed-off-by: Loic Poulain <loic.poulain@linaro.org>
There is no listen or accept for UDP, we need to enable the UDP
server mode (P5=1) as soon as bind is complete.
Signed-off-by: Loic Poulain <loic.poulain@linaro.org>
Secure Channel Base Key (SCBK) is a secret key used to derive the session
keys used to encrypt and decrypt OSDP packets. Secure coding practice
requires us to clear such sensitive data from stack once we are done
needing it. This patch addresses this issue.
Signed-off-by: Siddharth Chandrasekaran <sidcha.dev@gmail.com>
OSDP secure channel message blocks are terminated with a 0x80. This means
that even for zero length messages, we would have at least one block of
encrypted data to decrypt (since message blocks are rounded up to the next
16 byte boundary). The current length assertion checks for 16 byte
alignment but a malicious peer could send a specially crafted packet with
zero length blocks. Fix this issue by adding check for length == 0 case.
Signed-off-by: Siddharth Chandrasekaran <sidcha.dev@gmail.com>
HID readers are responding to a KEYSET command with an ACK in plaintext
instead of using the current session keys to acknowledge this command
(which is the reasonable thing to do as the command itself was received
encrypted with the old key). Since the spec doesn't say anything about
this, both methods are technically correct.
Make changes to CP so it allows ACKs in plaintext for KEYSET command in
particular and make the PD implementation do this too as it makes the code
look cleaner there (perhaps HID did it for the same reasons :D).
Signed-off-by: Siddharth Chandrasekaran <sidcha.dev@gmail.com>
If command or reply has no data, PD "should" use secure message types
SCS_15 or SCS_16. But some PD seem to not implement this correctly. We
will be tolerant towards those faulty implementations.
Signed-off-by: Siddharth Chandrasekaran <sidcha.dev@gmail.com>
OSDP command KEYSET is used to set the secure channel base key for all
connected PDs. This key is then used to derive the session keys for each
secure channel session. When the app wants to set the this key, it has
to issue a command and then both the CP/PD has to be notified of this
change so they can store this key in a non-volatile medium for future
operations across power cycles.
The current implementation of OSDP had limited support for key
management. This patch adds all the bells and whistles needed to handle
keyset command/event in the CP/PD application.
Signed-off-by: Siddharth Chandrasekaran <sidcha.dev@gmail.com>
Hoisting a `length--` helps simplify a lot of code which has ad-hoc -1s
in a bunch of places. Also, fix some formatting issues and remove
unnecessary log lines.
Signed-off-by: Siddharth Chandrasekaran <sidcha.dev@gmail.com>
The sample now support's setting up FAT FS on devices without
SD card access and this new ability requires update in documentation.
Signed-off-by: Dominik Ermel <dominik.ermel@nordicsemi.no>
The commits adds Kconfig option CONFIG_SAMPLE_FATFS_CREATE_SOME_ENTRIES
which causes the sample to attempt to create one file and one
directory, in case if listing does not show anything, just
to demnonstrate how FAT FS operations work on internal flash.
Signed-off-by: Dominik Ermel <dominik.ermel@nordicsemi.no>
The commits adds support for nrf52840dk_nrf52840 with two additional
configurations:
- with FAT FS on internal SoC flash
- with FAT FS on QSPI connected MX25
In case of SoC configuration there is re-configuration of internal
partitions done, doe to need for at least of 64kiB for FAT FS.
The QSPI configuration only defines additional partition on
external device.
Signed-off-by: Dominik Ermel <dominik.ermel@nordicsemi.no>
Provide a sample for ivshmem-doorbell running under virtualization
(QEMU). The sample relies on existing tools (ivshmem-server,
ivshmem-client) that must be run at the host (unix).
The sample can be run on userspace or kernelspace, and on arm64 (qemu,
kvm) and x86_64 (qemu) platforms.
This execution of this code is quite complex, thus the README should be
made available in the official documentation. This is why the code is a
sample and not a test.
Signed-off-by: Rodrigo Cataldo <rodrigo.cataldo@huawei.com>
Co-authored-by: Henri Xavier <datacomos@huawei.com>
The implementation of GIC v3 ITS uses k_aligned_malloc(), which will
only work if dynamic memory is available (system heap). Tell the user
that a dynamic memory pool is required.
The amount of memory will depend on registers probed during runtime.
Signed-off-by: Rodrigo Cataldo <rodrigo.cataldo@huawei.com>
Co-authored-by: Henri Xavier <datacomos@huawei.com>
The purpose of the GIC ITS is to translate message-passing interrupts into
LPIs. The LPI range starts at value 8192, which means the current default
value (200) is too low. Therefore, bump the highest IRQ number when ITS
is enabled.
Signed-off-by: Rodrigo Cataldo <rodrigo.cataldo@huawei.com>
Co-authored-by: Henri Xavier <datacomos@huawei.com>
Struct sh_telnet should be initialised before first function call.
Right now there is a possibility that telnet_accept function will
be called before memset.
Signed-off-by: Wojciech Slenska <wsl@trackunit.com>
Removed extra #includes at top of files. Missed closing } of
mec172xnlj.dtsi. Lower-cased 'reg' field of PWMs.
Signed-off-by: Jeff Daly <jeffd@silicom-usa.com>
The external flash chip is wired for QSPI. The chip, P25Q16H, has its
"Quad enable" bit in bit 9 of the Read Status Register (section 10.5 in
the datasheet), hence needs this particular quad enable requirement.
Co-authored-by: Marcin Niestroj <m.niestroj@emb.dev>
Signed-off-by: Oleg Ryjkov <oryjkov@gmail.com>
CFG register uses fields that are not defined in Synopsys databook of
Designware AHB DMA Controller.
Since current Zephyr code uses this driver only for the
intel_adsp_gpdma driver I assume that those fields are specific to
this DMA which is not the standard Designware one.
This patch allows to use either the standard Designware register or
the Intel one.
Signed-off-by: Sylvain Chouleur <schouleur@graimatterlabs.ai>
There are some issues with the current version of the code, mainly the
improper use of the internal OSC8M as a source for the DFLL48m without
division. The DFLL48M is designed to accept a maximum of ~33KHz
at it's input, as higher values will bring the multiplier down,
leading to instability.
Also added the following features:
* Support for external HF oscillator (XOSC)
* Support for crystal/external oscillators on XOSC32K/XOSC
* Automatic dividers/multiplier computation based on DT cpu frequency
* Support for user configurable NVM wait states
* Added option to skip clock (re)initialization (bootloader usecase).
Tests were performed on a custom SAMD20G18 board using different clock
sources and cpu frequencies.
Clocks were routed to GPIO pins and observed on a scope.
According to the datasheet, architecture is identical on D21/R21.
Due to the nature of the internal architecture and the fact that
DFLL48M is not really meant to output anything other than 48MHZ
some combinations of requested DT cpu frequency and source
frequency will not result in a perfect match.
Mostly insipred by the SAML21 implementation.
Signed-off-by: Ionut Catalin Pavel <iocapa@iocapa.com>
There is no need to use *_cmp_raw() functions here, all they do is cast the
pointers to in(6)_addr* and call the non-raw functions. Additionally, this
fixes a warning for the net_ipv6_addr_cmp_raw() call, which didn't cast the
arguments correctly.
Signed-off-by: Armin Brauns <armin.brauns@embedded-solutions.at>
Add interrupt and DMA tests for rpi_pico boards.
Add tests for combination of cases of DMA, interrupt and
DMA is not enabled by dts.
Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@fujitsu.com>
Syntacore RISC-V platforms have dedicated MTIMER_DIVIDER register which
should be configured during the Timer initialization.
The configuration of dedicated MTIMER_DIVIDER register could now
be performed during initialization if its address is provided.
Signed-off-by: Alexander Razinkov <alexander.razinkov@syntacore.com>
This change adds a mutex to protect against simultaneous access to the bus
instead of returning an error during transfers. Since most I2C code doesn't
handle retries (especially with a -EIO code) not blocking on a mutex can
cause a number of problems.
Signed-off-by: Corey Wharton <xodus7@cwharton.com>
move DT_DRV_COMPAT to bmp388.h. so that can be decide which
interface to use.
define struct bmp388_bus_io interface bmp388_i2c.c and bmp388_spi.c.
redefined bus operation interface in bmp388.c, this allow the driver
to decide which interface to use during construction
Signed-off-by: Weiwei Guo <guoweiwei@syriusrobotics.com>
Add check to ensure that CONFIG_MP_NUM_CPUS and CONFIG_MP_MAX_NUM_CPUS
are set the same. This will at least cause a build issue for out of
tree users.
Signed-off-by: Kumar Gala <kumar.gala@intel.com>
