The app_kernel test hangs or crashes on qemu_x86_64 when more than
one CPU is enabled. So limits the number of CPUs to 1 even when SMP
is enabled.
This issue has probably been masked for some time because the test
was previously marked as being "slow".
Signed-off-by: Martin Åberg <martin.aberg@gaisler.com>
The test now uses CONFIG_HAS_NEWLIB_LIBC_NANO rather than
toolchain_allow to determine if newlib nano is available.
Signed-off-by: Martin Åberg <martin.aberg@gaisler.com>
Upgrade board specification to use the VirtIO board.
Keeps FPU run-time support disabled since the RISC-V 64-bit FPU
support in kernel appears to be non-functional.
Signed-off-by: Martin Åberg <martin.aberg@gaisler.com>
The QEMU RISC-V VirtIO board is capable:
- 8 x CPU
- 256 MiB RAM
- PMP
- PCI
- ISA string: RVnnIMAFDCSU
- mul/div
- FPU with double precision
- MMU
- Compressed instructions
Devicetree was extracted from QEMU as described in virt.dtsi.
The same .dtsi SOC description is used for 32-bit and 64-bit.
Signed-off-by: Martin Åberg <martin.aberg@gaisler.com>
The CONFIG_FLOAT_HARD config previously enabled the C (compressed)
ISA extensions (CONFIG_COMPRESSED_ISA). This commit removes that
dependency.
Signed-off-by: Martin Åberg <martin.aberg@gaisler.com>
We compile objects with -mcmodel=medany. Now also give -mcmodel=medany
to the GCC front-end when linking to pick up the corresponding
multilibs.
Signed-off-by: Martin Åberg <martin.aberg@gaisler.com>
1. Exclude the CODE UNREACHABLE line while generating coverage report.
2. Exclude the memory domain deprecated API when calculating code
coverage.
Signed-off-by: Enjia Mai <enjiax.mai@intel.com>
1. Add a null dynamic name testing for device_get_binding().
2. Add a driver which initialization failed in SYS_INIT.
Signed-off-by: Enjia Mai <enjiax.mai@intel.com>
'reg' attribute removed from overall stm32l1 dts,
so eeprom size has to be specified for each SoC
in stm32l1x series.
Adds remaining stm32l1x SoCs that didn't have eeprom size specified yet.
Eeprom size added in stm32l151Xb-a & stm32l151X8-a dtsi files,
(based on device overview in datasheet DocID024330 Rev 5).
Eeprom size added in stm32l151Xb dtsi file (based on
device overview in datasheet DocID17659 Rev 12).
Signed-off-by: Noelle Clement <noelleclement@hotmail.com>
The main stack size is too small by default in many boards.
Increase the size to 1024 bytes which works fine with
sam_e70_xplained board.
Fixes#31343
Signed-off-by: Jukka Rissanen <jukka.rissanen@linux.intel.com>
1. Remove the error test cases that trigger assertion.
2. Refine the NULL and invalid kobject parameter test case.
3. Use the common fatal error handler to reduce code.
Signed-off-by: Enjia Mai <enjiax.mai@intel.com>
First, the maximum heap size must fit in 31 bits worth of chunks
because the internal 32-bit field holding the size is shared with
the `used` bit.
Then the mention of a 256-byte block in the doc is no longer
relevant. That pertained to the previous allocator implementation.
And ditto for the HEAP_MEM_POOL_MIN_SIZE kconfig option.
Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
Replace marco function, defined(), with IS_ENABLED() in host sub-devices
driver implementation. In this PR, we won't replace the macros which
cause -Wimplicit-function-declaration warning if related configuration
is not enabled or its type is not boolean..
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Allow vendor specific increase of user operation capacity for LLL, to
support queuing additional ticker operations from lower link layer
context. These would typically take place in lll_xxx_prepare.
Signed-off-by: Morten Priess <mtpr@oticon.com>
For Bluetooth Mesh, counter shall be increasing by one when
every try to establishing friendship.
Counter to be used when create friendship security material.
So this value shall be consist between friend and lpn.
Due to zephyr bluetooth mesh send previous counter, after that
it will automatically increase one, which will result in the
incorrect generation of friend key when key rephase.
Signed-off-by: Lingao Meng <menglingao@xiaomi.com>
Add test for the P4 Work Queue gadget. Includes coverage sections
detailing all elements of the API, and a reasonably extensive stress
suite that will saturate the device for 1k events.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
This adds a somewhat special purpose IPC mechanism. It's intended for
applications which have a "work queue" like architecture of discrete
callback items, but which need the ability to schedule those items
independently in separate threads across multiple CPUs. So P4 Work
items:
1. Can run at any Zephyr scheduler priority and with any deadline
(this feature assumes EDF scheduling is enabled)
2. Can be submitted at any time and from any context, including being
resubmitted from within their own handler.
3. Will preempt any lower priority work as soon as they are runnable,
according to the standard rules of Zephyr priority scheduling.
4. Run from a pool of worker threads that can be allocated efficiently
(i.e. you need as many as the number of CPUs plus the number of
preempted in-progress items, but no more).
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
Needing to check the current cycle time (which involves a spinlock and
register read on most architectures) is wasteful in the scheduler
priority predicate, which is a hot path. If we "burn" one bit of
precision (and document the rule), we can do the comparison without
knowing the current time.
2^31 cycles is still far longer than a live deadline thread in any
legitimate realtime app should ever live before being scheduled.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
The default of coredump is to dump all RAM as defined in
the linker script. However, this takes a while on boards
with bigger memory space, and would slow down automated
testing due to the need to grab all the data via serial.
So change it to dump minimal memory, as this would still
test the memory dumping capability.
Fixes#28547
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
In npcx7 series, the Timer and Watchdog module (TWD) generates the
clocks and interrupts used for timing periodic functions in the system.
It also provides watchdog reset signal generation in response to a
failure detection.
The CL also includes:
— Add npcx watchdog device tree declarations.
— Zephyr watchdog api implementation.
— Add Watchdog definitions for npcx7 series in
tests/drivers/watchdog/wdt_basic_api/src/test_wdt.c for
supporting test suites.
Signed-off-by: Mulin Chao <MLChao@nuvoton.com>
This commit is about the it8xxx2 i2c master driver which
includes six SMBus channels. The enhanced channel i2c3,
i2c4, i2c5 are controller which are designed to support
the I2C protocol.
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
Make sector size used by flash disk configurable and expose new disk and
fatfs configurations to Kconfig.
Signed-off-by: Markus Fuchs <markus.fuchs@de.sauter-bc.com>
Use these callbacks to send BTP events. They are useful for test
automation in auto-pts.
Signed-off-by: Michał Narajowski <michal.narajowski@codecoup.pl>
Until now, any attempts to call printk prior to early serial init has
caused page faults due to the device not being mapped yet. Add static
variable to track the pre-init status, and instead of page faulting
just suppress the characters and log a warning right after init to
give an indication that output characters have been lost.
Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
BLE and LwM2M grew in terms of RAM usage so that the sample does not
fit into nRF52832 anymore in the default configuration. This cause
twister to report an error when overflows errors are enabled.
Signed-off-by: Robert Lubos <robert.lubos@nordicsemi.no>
In order to ease reuse on other series, set DMA as optional
and use IT if no DMA channel is specified in the qspi node.
Tested on disco_l475_iot1
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Configure QSPI NOR support and MX25R6435F on disco_l475_iot1 board.
Set MX25R6435F as flash controller and arrange partitions to take
newlay available space into account.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Add device tree description for qspi node on STM32L4 and
signals on whole family.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Signed-off-by: Piotr Mienkowski <piotr.mienkowski@gmail.com>
Add support for DMA based STM32 QSPI NOR flash controller.
Driver configures both NOR flash and also QSPI hardware block.
Reuses existing jesd216 library.
QSPI hardware block handling is done through the use of Cube HAL API.
This requires the use of HAL interface also for DMA besides zephyr
DMA driver.
Zephyr DMA driver is used only for IRQ routing while HAL driver
handles the IP block. To achieve this it is required to:
-Configure both Cube and Zephyr drivers at init.
-Inform Zephyr driver that current channel handling will be done
by another instance and only a limited configuration should be done.
For this last part, a unused parameter is overridden in order to
transmit the information.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Signed-off-by: Piotr Mienkowski <piotr.mienkowski@gmail.com>
In preparation for QSPI DMA mode:
-Add a possibility to override driver by the HAL DMA. In that case
stream is set as busy and no configuration nor treatment is done.
In case of interrupt, flags clearing is let to HAL.
-Treat Half Transfer interrupt prior to Transfer Complete for the
cases were both IRQ are both raised at the time IRQ handler is called
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
