This modification is required to enable flash encryption.
Using hal implementation of spi_flash calls maintains
compability amongs different socs while offering
latest esp-idf enhancements.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
The original design intent with arch_sched_ipi() was that
interprocessor interrupts were fast and easily sent, so to reduce
latency the scheduler should notify other CPUs synchronously when
scheduler state changes.
This tends to result in "storms" of IPIs in some use cases, though.
For example, SOF will enumerate over all cores doing a k_sem_give() to
notify a worker thread pinned to each, each call causing a separate
IPI. Add to that the fact that unlike x86's IO-APIC, the intel_adsp
architecture has targeted/non-broadcast IPIs that need to be repeated
for each core, and suddenly we have an O(N^2) scaling problem in the
number of CPUs.
Instead, batch the "pending" IPIs and send them only at known
scheduling points (end-of-interrupt and swap). This semantically
matches the locations where application code will "expect" to see
other threads run, so arguably is a better choice anyway.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
The work queue has a semi/non-standard reschedule point implemented
using k_yield(), with a check to see if the current thread is
preemptible. Just call z_reschedule_unlocked(), it has this check
internally and is the intended API for this.
Really, this is only a half fix. Ideally the schedule point and the
lock release should be atomic[1] via the more idiomatic
z_reschedule(). But that would take some surgery, so let's go with
the simpler cleanup first.
This also avoids having to duplicate logic that gets added to
reschedule points by an upcoming patch.
[1] So that they represent a condition variable and don't race at the
end. In this case the race is present but benign, since the only thing
we really want to know is that the queue thread gets a chance to run.
The only cost is an occasional duplicated/needless context switch if
two threads are racing on a submit.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
add pin control nodes for LPC SOCs, to be filled with pin control
settings at the board level.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Includes the definition of the STM32_DMA_STREAM_OFFSET
depending on the peripheral to adjust the first DMA channel
in the list of streams.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
This defines the constant for the STM32_DMA_STREAM_OFFSET
to be 0 or 1 when counting the first DMA channel
depending on the stm32 soc and DMA peripheral version.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
This complements the Kconfig possibility, and allows setting an
interface as default on runtime. Changing the default interface also
works around limitations when trying to use an offloaded interface
together with a native one.
Signed-off-by: Ole Morten Haaland <omh@icsys.no>
User switch on mimxrt series boards requires a pull up resistor
to ensure the GPIO state does not float
Fixes#45129
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
In the EC application, the system may jump between two built Zephyr
images when necessary. When jumping from the current image to the other,
the firmware switches the eSPI-related pins to GPIO function at
initialization if define alt1_no_lpc_espi in def-io-conf-list.
It causes the eSPI to reset and breaks the eSPI communication after the
image jump. This patch prevents it by removing alt1_no_lpc_espi from
def-io-conf-list.
Signed-off-by: Jun Lin <CHLin56@nuvoton.com>
In the EC application, the system may jump between two built Zephyr
images when necessary. If we gate the eSPI clock at initialzation, it
will make the eSPI configuration which established by previous image
break and lost the communication between EC and host.
Signed-off-by: Jun Lin <CHLin56@nuvoton.com>
The LPC platforms define memory in SRAM blocks that can be
combined to represent larger memory blocks to the CPU. Change
the cpu0 allocation to use SRAM0-SRAM2 for 192K and change
cpu1 to use SRAM3-SRAM4 for 80K.
Signed-off-by: David Leach <david.leach@nxp.com>
The LPC platforms define memory in SRAM blocks that can be
combined to represent larger memory blocks to the CPU. Change
the M4 allocation to use SRAM0+SRAM1 for 128K.
Signed-off-by: David Leach <david.leach@nxp.com>
LPC platforms define multiple SRAM memory blocks that are contiguous
in memory but the zephyr build system doesn't have a method to
specify all the nodes to be used for a CPU's chosen "zephyr,sram"
node. To be able to get full use of memory, sram0 is redefined to
80KB in size.
Fixes#43872
Signed-off-by: David Leach <david.leach@nxp.com>
Adding a reference implementation of the Non-Volatile Memory module
needed to join any LoRaWAN network.
This NVM is based on the SETTINGS subsys to store all the required
key to join and communicate on a LoRaWAN network.
Without proper NVM, one may experience errors when using OTAA
to join the network, as the device may violate anti-replay
protection (depending on the version of LoRaWAN).
Signed-off-by: Giuliano Franchetto <giuliano.franchetto@intellinium.com>
remove existing SDMMC SPI driver, since it is replaced by the SPI mode
SD host controller driver.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
switch all in tree usage of zephyr,mmc-spi-slot to zephyr,sdhc-spi-slot.
This will change all boards to use the new SD subsystem instead of the
SDMMC SPI driver
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
with the legacy USDHC driver fully removed from the tree, the
nxp,imx-usdhc binding can now be used for the new SD host controller
driver.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
all in tree SOCs with the USDHC peripheral have now been converted to
use the new SD host controller USDHC driver, so remove legacy NXP disk
USDHC driver.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
added support for NXP iMX RT600/RT500 to use to SDHC driver, with SD
subsystem. Tested with RT685 EVK
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Add SDHC driver implementing spi mode support for SD cards. This driver
implements the standard SD host controller APIs, and sets the host
property "is_spi" to indicate to the SD subsystem the card will be
running in SPI mode.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Enable new USDHC driver for all RT10xx boards, since those will have
the SDHC driver selected by Kconfig
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Add SDMMC driver to subsystem. SDMMC driver will handle initialization,
as well as SDMMC I/O. SD mode support is currently supported, SPI mode
support is not.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
All SD cards require SD CMD0 (reset) and CMD8 (send IF cond) at boot.
Add this portion of the initialization flow to SD subsystem, as well as
query command to check if card is SDIO.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Add SD subsystem headers. SD subsystem contains generic header for SD
initialization, and headers for SDIO and SDMMC cards.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
SD host controller driver runs basic SD host controller tests, including
checking SD presence, and sending commands to SD card. No data transfer
is performed.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
