There were some inconsistencies in flash memory for both
of these boards where they do not match their stated specs.
This commit fixes the inconsistencies.
Signed-off-by: Nicolas Munnich <nickmunnich@gmail.com>
Define PWM LED at nRF54L20pdk board definition.
Set status=okay for pwm20 node.
Add pincontrol for pwm20:OUT0 at P1.07 (LED1).
Add pwm_led1 node.
Add alias pwm-led0.
Signed-off-by: Sebastian Głąb <sebastian.glab@nordicsemi.no>
Enable Twister tests of PWM driver on nrf54l20pdk.
Overlays were already added to PWM tests.
Signed-off-by: Sebastian Głąb <sebastian.glab@nordicsemi.no>
Add wifi_spi label to nRF54h and nRF54l dts files to help
in shield overlay files
Signed-off-by: Bansidhar P.M <bansidhar.mangalwedhekar@nordicsemi.no>
This commit adds multicore support for RT1180.
It enables the secondary core CM7 to be copied from flash
and run from RAM.
Signed-off-by: Tomas Galbicka <tomas.galbicka@nxp.com>
In 923d313a04 the clock frequency in DTS
for the UART00 was fixed, but not for the simulated target. This was
likely due to the HW models modeling it as 16MHz instead of 128MHz for
this particular one as it is in reality.
Now that the HW models have been fixed, let's let this clock be
configured like for real HW.
Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
This commit reverts using of cpu1_partition because it is
taking space from slot0 and slot1 partitions.
For now use slot1 partition for cpu1.
Signed-off-by: Tomas Galbicka <tomas.galbicka@nxp.com>
This reverts commit 70419bdee7.
This is because there are issues around slow IPC thoughput
with icbmsg, which is causing issues with BLE when lots of
data is required to be exchanged, e.g. with ISO.
Also there is an assert icmsg.c#L190 which occurs when
initializing bluetooth and IPC in certain circumstances.
Signed-off-by: Sean Madigan <sean.madigan@nordicsemi.no>
The PAN B511 evaluation board is a development tool for the
nRF54L15 from Nordic Semiconductor.
Signed-off-by: Steffen Jahnke <steffen.jahnke@eu.panasonic.com>
The stm32f4_disco board features an audio codec (cs43l22) connected to
an audio jack (TRS) output, and to the stm32f4 via I2S and I2C. To set
this up, several peripherals must be configured:
- Enable I2S3 and the PLLI2S (tuned for 22.05/44.1/88.2 kHz audio)
- Enable DMA1 (used by I2S3)
- Enable I2C1, and add definition for the CS43L22 on the bus
- Disable USART1 and CAN1 which have conflicting pinctrl with I2C1
This new setting is more appropriate, because this gives access to the
audio jack output by default (instead of "bare" pins not connected to
anything on the board).
Signed-off-by: Titouan Christophe <moiandme@gmail.com>
The current implementation requires SoCs/Boards to manualy instantiate
the preripherals and initilize them.
The change lets Zephyr rely on the device tree setup to instantiate &
initialize the relevant gpio peripheral.
Signed-off-by: Wilfried Chauveau <wilfried.chauveau@arm.com>
Add OTGFS peripheral to the stm32h7rs soc series, and enable it on the
Discovery board STM32H7S78-DK, where it is wired to USB Type-C port 2.
Signed-off-by: Titouan Christophe <moiandme@gmail.com>
Add USB support on USBFS port on these boards:
- RA8: ek_ra8m1, ek_ra8d1, mck_ra8t1
- RA6: ek_ra6m1, ek_ra6m2, ek_ra6m3, ek_ra6m4, ek_ra6m5
- RA4: ek_ra4m2, ek_ra4m3, voice_ra4e1
Signed-off-by: The Nguyen <the.nguyen.yf@renesas.com>
Selecting the wrong power scheme could potentially destroy the board.
Luckily, the bit can only be set once and the default build still
uses the Arduino bootloader (which has the correct setting).
Signed-off-by: Martino Facchin <m.facchin@arduino.cc>
Switches the default revision of mimxrt1170_evk from A to B.
Customers can only purchase MIMXRT1170-EVKB.
Revision "A" is obsolete and unavailable.
Signed-off-by: Andrej Butok <andrey.butok@nxp.com>
A follow-up to commit fe87abe0b9
This addresses boards that had pending pull requests
at the time the initial clean-up was done.
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
Add the memory region reserved in DRAM for VirtIO and Vring data
for IPC. Add this as the default chosen zephyr,ipc_shm.
Signed-off-by: Andrew Davis <afd@ti.com>
Add the memory region reserved in DRAM for VirtIO and Vring data
for IPC. Add this as the default chosen zephyr,ipc_shm.
Signed-off-by: Andrew Davis <afd@ti.com>
Add the memory region reserved in DRAM for VirtIO and Vring data
for IPC. Add this as the default chosen zephyr,ipc_shm.
Signed-off-by: Andrew Davis <afd@ti.com>
Currently the resource table is added to the memory-region labeled DDR.
This region can also be extra space for code/data, although this is
not yet implemented. This will mean that the linker is free to put
the resource table *after* the code/data sections in DDR. The resource
table must be at the start of the assigned DRAM area for the remote
core to support early-boot/late-attach usecases.
To solve this, we carveout the first 4KB of our DRAM area specifically
for the resource table. This matches how this issue was solved for the
K3 R5F cores.
To make this clear we label this memory-region "RSC_TABLE". This is
done at the linker file level, which is common for all K3 M4 boards
and so we update all 3 such boards in this one patch instead of
patch-per-board.
Signed-off-by: Andrew Davis <afd@ti.com>
This commit adds a missing default value for the `DCHACHE_LINE_SIZE` option
for the `qemu_xtensa/sample_controller32/mpu` platform. This is required
after 8b39d4a613 added a build assert
checking this value against `core-isa.h` from Xtensa HAL.
Fixes#85591.
Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
Taking a look at the schematic shows that
tx-enable-gpios and dio2-tx-enable were directly connected.
This had the effect tx-enable-gpios was trying to pull the line down
while SX1262 is pulling the same line high. This increased
the power consumption.
Now only the SX1262 sets the antenna to tx via dio2-tx-enable.
Setting the antenna to rx is still done via the rx-enable-gpios.
The antenna defaults to rx if not in use.
Signed-off-by: Carlo Weidinger <carlo.weidinger@protonmail.com>
Add Clock Control support for board RZ/G3S-SMARC
Signed-off-by: Tien Nguyen <tien.nguyen.zg@renesas.com>
Signed-off-by: Nhut Nguyen <nhut.nguyen.kc@renesas.com>
