I2S driver was merged after interrupt .dtsi was changed,
causing CI to fail. This updates it accordingly.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Add definition of the nRF9280 SiP with its Application,
Radio, and Peripheral Processor (PPR) cores and a basic set
of peripherals: GRTC, GPIOs, GPIOTE, and UARTs and few others.
Signed-off-by: Emanuele Di Santo <emdi@nordicsemi.no>
Co-authored-by: Andreas Moltumyr <andreas.moltumyr@nordicsemi.no>
Device tree configuration for USB serial node and clock control
fix for proper device initialization.
Signed-off-by: Raffael Rostagno <raffael.rostagno@espressif.com>
Between SoC revisions, the address was moved from 0x5F909000 in the
global domain, to 0xF0000000 in PPR's private address space.
Move the corresponding DT node out of `cpuppr_vpr` range to a separate
bus node, which is considered inaccessible to all cores but `cpuppr`.
This is expressed by selectively leaving out the `simple-bus` compatible
and `ranges` property, i.e., they're only set in `nrf54h20_cpuppr.dtsi`.
This lets the interrupt controller node remain visible at system level,
for the purpose of describing IRQ mappings between cores in devicetree.
Signed-off-by: Grzegorz Swiderski <grzegorz.swiderski@nordicsemi.no>
Rename it from litex,eth to litex,liteeth
to reflect the new name of the driver.
Zero got removed from the litex
ethernet compatible, as it now supports
multiple instances.
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
remove litex,sys-clock-frequency from litex,clk,
because we already define that in the clock-frequency of cpu0.
This can be accessed via
CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC.
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
According to the RV32M1 Series Manual, Rev 1.1 RV32M1 series supports the C
extension, and doesn't support the A extension. Apply fixes accordingly.
Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
After changing the VEVIF and BELLBOARD names,
the dts for the individual boards must be aligned.
Signed-off-by: Jakub Zymelka <jakub.zymelka@nordicsemi.no>
Kconfig, .ld and comments fixing
Fixed address of UART1, WDT and RTC timer disabled by default
Signed-off-by: Raffael Rostagno <raffael.rostagno@espressif.com>
Update the native controller to the new HCI driver API. The devicetree
node is placed under existing `radio` nodes, which seemed like the most
intuitive option.
Signed-off-by: Johan Hedberg <johan.hedberg@gmail.com>
Add the property of drive-strength to drive a high or low current
selection. If this property is not configured, it is the default
setting. According to the SPEC, the default drive current selection
varies from different pins.
Define the high level 0b: 8mA
low level 1b: 4mA or 2mA
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
This WDT is responsible for monitoring the external
32.728 Hz crystal connected to pins XTAL_32K_P and
XTAL_32K_N. If an oscillation failure is detected
the hardware automatically switch to RTC_RC_SLOW
clock source and triggers an interrupt.
Signed-off-by: Lucas Tamborrino <lucas.tamborrino@espressif.com>
The RTC subsystem in espressif's SOCs, among other tasks
is responsible for clock selection for CPU and for low
power domain clocks such as RTC_SLOW and RTC_FAST.
This commit allows for proper clock source and rate
selection for CPU, using the espressif,riscv and
espressif,xtensa-lx6/7 bindings.
It also enables clock selection for RTC_FAST and RTC_SLOW,
that impacts some peripherals, such as rtc_timer.
Signed-off-by: Lucas Tamborrino <lucas.tamborrino@espressif.com>
This commit makes the devicetrees of the targets that are based on the QEMU
`virt` machine more consistent with the rest of the RISC-V targets in
Zephyr by:
* adding the `riscv,isa` property
* adding a compatible string which uniquely identifies the `virt` core
Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
Chip it82xx2 series change the HW sha module and it82xx2 series
can't use original sha driver anymore, so move sha0 node from
it8xxx2 to it81xx2 series.
Signed-off-by: Ruibin Chang <Ruibin.Chang@ite.com.tw>
