This commit adds driver support for ADC1 on all 8 supported series of
stm32 with resolution and conversion time selection and calibration.
Currently DMA is not supported for all series, and without it, zephyr
won't be able to catch up ADC's end of conversion interrupt, so this
version of the driver supports one channel conversion only. Users want
multi-channel conversion should use multiple sequences in their app
code.
This driver uses LL lib rather than HAL because the current HAL lib for
ADC will call HAL_DMA_* functions rather than using zephyr's common DMA
interface, so that way the driver will break the consistency of the
code.
This driver has been tested on multiple nucleo boards including
NUCLEO_F091RC/F103RB/F207ZG/F302R8/F401RE/F746ZG/L073RZ/L476RG and all
passed the test cases in tests/drivers/adc/adc_api. If the external ADC
line is floating, it may fail the tests since ADC may get 0V and the
test cases think 0 is failing. Connect it to any voltage source between
0-3.3V will help passing the test cases.
Signed-off-by: Song Qiang <songqiang1304521@gmail.com>
Provides a STM32 RTC driver using new counter API.
Driver does not support wrap related functions (set, get, ..)
Fixes#11373
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
exti driver implementation does not fit all SoCs because
some EXTI ip does not match stm32_exti register map provided.
Instead of providing exti register map for all SoCs, use LL API
which abstracts IP variations and enable uniform use of the drivers
on all STM32SoCs.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Clean up a left over from GPIO driver factorization.
Definition of GPIO_REG_SIZE and GPIO_PORTS_BASE do not need anymore
to be spread accross SoCs.
Put these definitions directly in STM32 pinmux driver.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
The original implementation of gpio functions access registers
directly. Using LL library can add a set of unifying access
functions for all series of stm32 for avoiding accessing low level
code, and improve readability.
Signed-off-by: Song Qiang <songqiang1304521@gmail.com>
On STM32L4, 14 pins (Port G[15:2]), require external power supply.
Activate this at port G init when PWR_CR2_IOSV is defined.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Add support for Low Speed External 32.768 kHz oscillator (LSE ).
Add support for MSI PLL-Mode offering an automatic calibration feature
in combination with the LSE. This allows the MSI to reach an accurate
+/-0,25% clock perfectly suitable for USB full-speed clock.
Signed-off-by: Loic Poulain <loic.poulain@linaro.org>
Move the SoC outside of the architecture tree and put them at the same
level as boards and architectures allowing both SoCs and boards to be
maintained outside the tree.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2018-09-13 00:56:48 -04:00
Renamed from arch/arm/soc/st_stm32/stm32l4/soc.h (Browse further)
