For proper operation of QUADSPI IP block, both sides of communication;
NOR flash memory and STM32 controller need to support 4 IO
transmission.
After this change the QSPI stm32 driver is able to program NOR flash
memory to switch itself to use all 4 IO lines (SIO[0123]) to transmit
and receive data.
The QE bit (in SPI-NOR's Status Register) is the non-volatile one, so
setting it is done only once (at first boot of the device).
Signed-off-by: Lukasz Majewski <lukma@denx.de>
Some flash memories connected to QUADSPI IP block on stm32[fh]7 devices
require proper reset pulse before configuration.
This patch adds two new properties - the 'reset-gpios' phandle,
which allows specifying GPIO pin for RESETn pulse and
'reset-gpios-duration', which provides the time (in ms) for reset
duration.
Signed-off-by: Lukasz Majewski <lukma@denx.de>
The 'flash-id' property defines the number of QSPI's dedicated GPIO
bank (and flash ID), which will be used to communicate with flash
memory.
For example, on stm32h7xx it is possible to use 'quadspi_bk1_*' and
'quadspi_bk2_*' set of pins, so one may need to select between them
when required.
By default - pins from 'quadspi_bk1_*' bank are used, so the
'flash-id = <2>;' property, when your use case (e.g. PCB design)
requires it, forces usage of 'quadspi_bk2_*' pins.
Signed-off-by: Lukasz Majewski <lukma@denx.de>
The PINCTRL_DT_(INST_)DEFINE macros already defined the trailing ;,
making its usage inconsistent with other macros such as
DEVICE_DT_DEFINE.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Replace usages of DT_PARENT(DT_DRV_INST(idx)) with more idiomatic
DT_INST_PARENT(idx).
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
All the macro for dma-cells are now in the
include/drivers/dma/dma_stm32.h header file.
So the include/dt-bindings/dma/stm32_dma.h is no more
useful and removed from #include.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Since we removed various series headers, move stm32 driver
under main driver/pinmux folder.
Take this change into account into various drivers.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
flash_write_protection_set() API was deprecated so driver
implementation interface is left behind as well.
This patch removes all implementation pointed by the interface
'struct flash_driver_api.write_protection'.
Signed-off-by: Andrzej Puzdrowski <andrzej.puzdrowski@nordicsemi.no>
Flash write protection services were integrated into erase and write
procedures. This is step required for fixing following issue:
Multi-threading flash access is not supported by
flash_write_protection_set().
flash_write_protection_set() will be deprecated
Signed-off-by: Andrzej Puzdrowski <andrzej.puzdrowski@nordicsemi.no>
Convert from device_get_binding to DEVICE_DT_GET. In doing this we
no longer need the label in the devicetree node so we remove that.
Removed all __ASSERT_NO_MSG(clk) since we'll get a build error if
DEVICE_DT_GET cant be satisfied, and the clock control api's will
handle reporting if the device_is_ready.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
In order to ease reuse on other series, set DMA as optional
and use IT if no DMA channel is specified in the qspi node.
Tested on disco_l475_iot1
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Add support for DMA based STM32 QSPI NOR flash controller.
Driver configures both NOR flash and also QSPI hardware block.
Reuses existing jesd216 library.
QSPI hardware block handling is done through the use of Cube HAL API.
This requires the use of HAL interface also for DMA besides zephyr
DMA driver.
Zephyr DMA driver is used only for IRQ routing while HAL driver
handles the IP block. To achieve this it is required to:
-Configure both Cube and Zephyr drivers at init.
-Inform Zephyr driver that current channel handling will be done
by another instance and only a limited configuration should be done.
For this last part, a unused parameter is overridden in order to
transmit the information.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Signed-off-by: Piotr Mienkowski <piotr.mienkowski@gmail.com>
