This patch adds new support for SiFive HiFive Unleashed which has
SiFive FU540 SoC, DDR and some peripherals.
This is first version so not support all features of the board.
Signed-off-by: Katsuhiro Suzuki <katsuhiro@katsuster.net>
This patch adds support for SiFive Freedom U540 SoC.
First version is minimum only using UART, SPI and DDR memory area.
Signed-off-by: Katsuhiro Suzuki <katsuhiro@katsuster.net>
This patch changes condition of 'depends on' of sifive UART driver
to support other SoCs of SiFive Freedom series.
Signed-off-by: Katsuhiro Suzuki <katsuhiro@katsuster.net>
This patch fixes printf format specifier "%u" -> "%zu" for printing
an argument of size_t on 64bit environment.
Signed-off-by: Katsuhiro Suzuki <katsuhiro@katsuster.net>
add board support for Dragino NBSN95 NB-IoT sensor
node. Initial support only includes UART (with followup
patches on BC95 and other peripherals)
Signed-off-by: Parthiban Nallathambi <parthiban@linumiz.com>
Trivial change for C++, reorder Z_MEM_SLAB_INITIALIZER members
initialization in the same order they are defined in k_mem_slab
structure.
Fixes#38219
Signed-off-by: Lucas Dietrich <ld.adecy@gmail.com>
Add a very simple application intended to show how to use the Audio
DMIC API and also to be an aid in developing drivers to implement
this API.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Add a shim that allows using the nrfx PDM driver via the Zephyr API.
Add also missing devicetree nodes representing the PDM peripherals
in the nRF52 Series SoCs.
Extend the "nordic,nrf-pdm" binding with a new property that allows
specifying the clock source to be used by the PDM peripheral (so that
it is possible to use HFXO for better accuracy of the peripheral clock
or, in the nRF53 Series SoCs, to use the dedicated audio oscillator).
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
The name pinmux is misleading, since no actual pinmuxing is done (just
pull-up setup).
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
The internal pinmux API was being used to setup GPIO pull-ups, however,
this can be done using the standard GPIO API.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
After the Technical Steering Committee decided to approve the transition
from Slack to Discord, it is necessary to update all the documentation
to reflect this change.
Signed-off-by: Carles Cufi <carles.cufi@nordicsemi.no>
The free run timer will be used to count before entering hibernate
mode. Move the related registers to the head file for accessing.
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
Zephyr now requires CMake 3.20 or newer.
Let's remove comment regarding ADDITIONAL_CLEAN_FILES only supported
with CMake 3.15 or newer.
Also remove the ADDITIONAL_MAKE_CLEAN_FILES which provided the same
functionality, but only for Makefiles when using CMake <3.15.
Signed-off-by: Torsten Rasmussen <Torsten.Rasmussen@nordicsemi.no>
The `set_conf_file()` was deprecated in
6d4ba3490f
which is before Zephyr v1.14 LTS.
Let's remove the support now, before releasing a new LTS.
Signed-off-by: Torsten Rasmussen <Torsten.Rasmussen@nordicsemi.no>
This feature got written twice for two different purposes (to inform
the SOF app of which CPUs are running, and to predicate the delivery
of IPIs to the cores ready to receive the interrupt). Use only one.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
When working with the SOF kernel driver, it likes to shut down the DSP
on error. That means there is a very small window in which to catch
any log output, even with a whiteboxed kernel. So we should be
polling much faster (10 Hz) for changes when we detect a reset.
Also, don't repeatedly log the device reset detection, it spams the
console badly when we crank up the rate. Just log it once and then
stay silent until we see output.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
These are getting build failures due to some kind of devicetree
console definition missing. These devices don't do networking, and
strictly don't even have a proper console device (logging is done via
a host mechanism). Probably fixable. Not worth the trouble. Filter.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
On pre-2.5 cAVS, the initial IDC interrupt to start the other core is
handled by software in the firmware ROM. That means that it has to be
unmasked for the mechanism to work (with 2.5, the interrupt is handled
by hardware regardless of what the masking state in the interrupt
controller is).
Similarly, the Xtensa Region Protection Option entries have already
been set by ROM code when we arrive in enable_l1_cache(), so we can
skip that part on older machines. Also removed because trying to
rewrite those entries was causing inexplicable hangs on cAVS 1.5,
plausibly because the region had active cache lines.
(This patch is separate for easier review in a long evolving PR.
Technically it represents a bisection problem as the "New IDC Driver"
patch before this was a regression. Seems like a safe enough thing to
handle if you land on this.)
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
Fix various bugs with the new IDC layer that show up in edge cases
where code relies on correct timing of IPIs (unsurprisingly there is a
lot of code that recovers anyway even if the IPI doesn't arrive
promptly). Leaving this as a separate patch because the prior code in
the PR has already been reviewed and it "mostly" worked:
The unmasking of the L2 interrupt bit (remember there are three layers
of masking of the IDC interrupt) was always operating on CPU0 at CPU
startup because the code had been copied blindly. Unmask the CPU
we're actually launching. It turns out cAVS 2.x re-masks this on CPU
launch automatically.
The global init code to unmask all these interrupts at startup had the
same bug, even though it turned out to be needless (the initialization
state has it unmasked until it turns it back off). Do it right
anyway. Similarly add code to clear out existing interrupt latch
state by ACKing all IDC interrupts at startup. Seems needless, but
behavior isn't documented so let's be safe.
Flag CPU0 as always "active" for the purposes of IPIs. Forgot to do
this earlier, oops.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
The alignment on .bss was coming out wrong. The ". = ALIGN(4096);"
statement was being ignored, somewhat inexplicably. This resulted in
the bss symbols being assigned corret-seeming, non-overlapping
addresses. But it overlapped the page-sized padding at the end of
.data.
As it turns out, the rimage format (not the linker or Zephyr) requires
page-sized sections to copy, and the bootloader code does that copy by
writing to the CACHED mapping of the memory (.bss is, like .data,
uncached/coherent by default). So at runtime the CPU was running in a
context where the cache was populated with "booby trap" data at the
start of .bss. True .bss access would hit the memory uncached and see
the "correct" value, but at arbitrary times during execution lines
would be flushed out of L1 cache on top of it.
Oops. This was found by accident, actually, as routine changes to the
linker script to correctly support the case where KERNEL_COHERENCE=n
(i.e. put everything in the cached mapping and nothing in uncached)
suddenly hit rimage failures because of the overlap.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
New docs for cavs_v25 describe building a Linux kernel for a
Chromebook and need to talk about these kconfigs.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
Add a SOC API to allow for application control over deep idle power
states. Note that the hardware idle entry happens out of the WAITI
instruction, so the application has to be responsibile for ensuring
the CPU to be halted actually reaches idle deterministically. Lots of
warnings in the docs to this effect.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
There is a hardware startup state where power gating can be "enabled"
even though the core is actually launchable via an IDC interrupt (in
fact that's the hardware default). In that state, the CPU will launch
correctly but then unexpectedly shut itself off then it enters the
idle thread.
Don't rely on initialization state, always set the power and clock
gating bits (to disable gating) immediately before CPU launch.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
Add a struct-based interrupt masking API to match the existing shim
and IDC register interfaces. The existing interrupt controller code
isn't using it yet.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
A simple WAITI isn't sufficient in all cases. The cAVS 2.5 hardware
uses WAITI as the entry state for per-core power gating, which is very
difficult to debug. Provide a fallback that simply spins in the idle
loop waiting for interrupts to provide a stable system while this
feature stabilizes.
Also, the SOF code for those platforms references a known bug with the
Xtensa LX6 core IP (or at least some versions), and will prefix the
WAIT instruction with 128 NOP.N's followed by an ISYNC and EXTW. This
bug hasn't been seen under Zephyr yet, and details are sketchy. But
the code is simply enough to import and works correctly.
Place both workaround under new kconfig variables and select them both
(even though they're actually mutually exclusive -- if you select both
CPU_IDLE_SPIN overrides) for cavs_v25.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
On CPU startup, When we reach the cache flush code in arch_switch(),
the outgoing thread is a dummy. The behavior of the existing code was
to leave the existing value in the SR unchanged (probably NULL at
startup). Then the context switch would walk from that address up to
the top of the outgoing stack, flushing everything in between. That's
wrong, because the outgoing stack is a real pointer (generally the
interrupt stack of the current CPU), and we're flushing everything in
memory underneath it.
This also reverts commit 29abc8adc0 ("xtensa: fix booting secondary
cores on the dummy thread"), which appears to have been an early
attempt to address this issue. It worked (modulo all the extra and
potentially incorrect flushing) on cavs v1.5/1.8 because of the way
the entry code worked there. But on 2.5 we now hit the first context
switch in a case where those extra lines are in address space already
marked unwritable by the CPU, so the flush explodes.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
On cAVS 2.5, there is an inherent race with the IDC interrupt. It's
used for routine IPIs during OS operation, but also for launching a
power-gated core. Recent changes moved the unmasking of the IDC
interrupt earlier, which made it possible for early OS scheduler
behavior (e.g. adding the main thread to the run queue) to
accidentally launch the other cores into LP-SRAM that had not been
initialized.
Instead of treating this with initialization ordering, keep and
maintain a list of active CPUs and check them at runtime to be sure we
never try to IPI a CPU that isn't running yet. We're going to need
this feature when we add live core offlining anyway.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
Use the built-in IDC handling and not IPM (which is limited to two
CPUs). Declare two cpus for now, Zephyr tests are having problems
with more at the moment (that isn't a CI configuration, so we may have
work to do).
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
The original interface for the intra-DSP communication hardware on
these devices was buried inside a Zephyr IPM implementation.
Unfortunately IPM is a two-endpoint point-to-point communication
layer, it can't represent the idea of devices with more than 2 cores.
And our usage (to push a no-argument/no-response scheduler IPI) was
sort of an abuse of that metaphor anyway.
Add a new IDC interface at the SOC layer, borrowing the C struct
convention already used for the DSP shim registers.
Augment with extensive documentation, extracted via a ton of
experimentation on cAVS 2.5 hardware.
Note that this leaves the previous driver in place for the cavs_v15
and intel_s1000 devices. In principle they should use it too (the
hardware registers are identical), but this hasn't been validated yet.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
Earlier platforms were relying on the system ROM to have done this
correctly, but with CAVS 2.5 we launch the CPU into our own code
directly. So we need to do those steps manually. And there's also a
new one on this hardware, which has software power control over the
cache SRAM.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
Hardware defaults for the secondary CPUs have the S32C1I instruction
set to be atomic only with respect to the local L1 cache, which is
basically useless on a multiprocessor platform. The CPU0 boot path
sets this manually, so we need to duplicate that here.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
On MP cores that don't come through the core entry point
(e.g. TGL/v2.5) we reach C code with hardware defaults for the RPO/TLB
settings. Set these up correctly on entry.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
This hardware works a little differently. The cores will start up
immediately on receipt of an IDC interrupt (they don't need the host
to be involved), but they don't have a ROM. They start executing at
the start of the LP-SRAM block always. Copy over a tiny trampoline
for them that jumps to the existing multiprocessor startup path.
Also set the PS WOE bit to enable register windows in the startup
path. This isn't the hardware default, and where the ROM would do
that for us before here we need to make sure it's on.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
This reverts commit ee7773fb46.
Unfortunately this mechanism doesn't seem to actually work on the SDK
linker. The emitted sections, when passed a symbol name as the "start
address" just appear wherever the "." variable was pointing (in this
case, into the cached region). That breaks the kernel coherence
layer, obviously.
Revert for now, which will regress the XCC build fix pending a proper
root cause.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
This aligns the SoC initialization with the one in SOF,
especially the manipulation of clock control and power control
registers. These registers are not entirely the same across
CAVS versions, so we need to deal with them according to
which version we are building for. This also consolidates
the macros for these registers to the one provided by SOF
(soc/shim.h) to avoid duplication. Another note is that
the usage of clock gating bit was not correct. In SOF,
clock gating of SoC cores should be allowed but the old code
in Zephyr prevented clock gating, which has the potential to
prevent the whole DSP from going into low power mode.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
The wall clock timer is not (per documentation) part of the
"timestamping" register set on the DSP. And its counter and
comparator registers work fine always. But if the DSP isn't set as
the "owner" of the timestamp hardware, wall clock interrupts never
arrive.
Also grab the PLL ownership too, because SOF already does anyway.
While we don't have a dynamic clock driver yet, we will surely want
one soon and will needt this.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
These windows control host visibility of the trace output buffer. The
buffer itself is writable memory always, but until we get to the
register init the host can't see them. Since they contain
printk/logging output, they REALLY need to be initialized earlier than
anything else.
Also remove a rogue memset of the trace buffer. That buffer is
already being initialized in a lazy-evaluated way by the trace output
code, and blowing it away here has the effect of forgetting anything
earlier code was trying to log!
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
The default development environment for this target is in fact a
consumer Chromebook available to anyone. So it deserves public
documentation.
Note that this spends considerably more time explaining the details of
how to configure a chromebook as a Zephyr development platform than it
does the process for building and running Zephyr (which is really very
conventional). Chromebooks, which allow user-signed audio firmware,
are a great boon to SOF development. But they were never intended as
developer devices themselves.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
Add a loader script variant for Tiger Lake (cAVS 2.5) devices, which
have very slightly different loading behavior from older 1.5 DSPs.
This is added as a "-v25.py" script, and the original has been renamed
to cavs-fw-v15.py. Note that there is no good reason except schedule
pressure that these are not the same script, I just wasn't able to
make a single script work compatibly in the time available.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
Add support for the extended manifest blocks that recent versions of
rimage are including as a prefix on the firmware blob.
Also include some PCI runtime PM tricks to reliably enable the DSP
device on kernels that have turned off the DSP device automatically
(e.g. systems that have PM enabled by default but where the SOF driver
is not loaded -- chromebooks work this way, potentially other
distros).
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
Zephyr Bluetooth Mesh move adv send cb to buf destructor
callback, There are two net_buf_pool define, one to adv.c
and ore to friend.c, we are missing destructor in friend.c.
Signed-off-by: Lingao Meng <menglingao@xiaomi.com>
Two checks reported wrong value if the value was invalid.
CIS parameter check would always fail on correct values
due to missing negation of valid_chan_qos.
Signed-off-by: Emil Gydesen <emil.gydesen@nordicsemi.no>
Fix two typos in documentation, one in a sample's comment, and one in a
sample's console message. Found while learning Zephyr and exploring the
sources.
Signed-off-by: Nikolai Kondrashov <spbnick@gmail.com>
Adds flash partitions and chosen nodes to the mimxrt1024_evk device tree
to support mcuboot on the internal QSPI flash.
Also adds missing zephyr,itcm chosen node.
Also enables FlexSPI flash driver XIP mode support on this board to
support mcuboot.
Signed-off-by: Mikkel Jakobsen <mikkel.aunsbjerg@prevas.dk>
add correct binding, fix size to 32MBit, add erase and write
block size to support mcuboot and rename to reflect the actual
flash model.
Signed-off-by: Mikkel Jakobsen <mikkel.aunsbjerg@prevas.dk>
