Refactors all of the serial drivers to use a shared driver class
initialization priority configuration, CONFIG_SERIAL_INIT_PRIORITY, to
allow configuring serial drivers separately from other devices. This is
similar to other driver classes like I2C and SPI.
The default is set to CONFIG_KERNEL_INIT_PRIORITY_DEVICE to preserve the
existing default initialization priority for most drivers. The one
exception is uart_lpc11u6x.c which previously used
CONFIG_KERNEL_INIT_PRIORITY_OBJECTS.
This change was motivated by an issue on the frdm_k64f board where the
serial driver was incorrectly initialized before the clock control
driver.
Signed-off-by: Maureen Helm <maureen.helm@intel.com>
This kconfig option enables runtime configuration of UART
controllers. This allows application to call uart_configure()
to configure the UART controllers and calling uart_config_get()
to retrieve configuration. If this is disabled, UART controllers
rely on UART driver's initialization function to properly
configure the controller. The main use of this option is mainly
code size reduction.
Fixes#16231
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Use TX FIFO level interrupt if available in hardware. It matches the
Zephyr UART API and avoids "bootstrapping" which is needed when using
the TX edge interrupt ("TI"). TX FIFO has room for up to 32 characters
and will typically reduce the number of interrupts.
Details:
APBUART can be synthesized with or without support for TX/RX FIFO.
Edge interrupts which fire when TX holding register changes and RX data
available are always available, independent of the FIFO configuration.
If FIFO is made available at synthesis time, two additional interrupts
become available: TX FIFO half-empty and RX FIFO half-full. These
are level interrupts.
Signed-off-by: Martin Åberg <martin.aberg@gaisler.com>
This commit aligns the GRLIB APBUART driver with the Zephyr UART API
and fixes an issue where TX interrupt could previously be lost. It
was typically seen during interactive operation in the Zephyr shell.
There is an expectation in the Zephyr UART API that TX ready (i.e. TX
buffer space available) interrupt is a level interrupt, i.e. always
active while there's TX buffer space available. In particular, there's
an expectation that after uart_irq_tx_enable(), the TX interrupt will
immediately fire (assuming free TX buffer space is available).
The APBUART "Transmitter interrupt (CTRL_TI)" does not directly fulfill
this expectation because it is edge triggered and fires when the TX
holding register moves from being non-empty to empty. The solution
is to "bootstrap" interrupt processing by calling user-defined ISR
in irq_tx_enable().
This fix is similar to commit 49bb163756 ("drivers: serial:
uart_cmsdk_apb: Fix interrupt-driven operation").
Signed-off-by: Martin Åberg <martin.aberg@gaisler.com>
Adds driver support for APBUART transmitter and receiver
interrupts. Compatible with APBUART implementations without HW FIFO
interrupt, for example QEMU.
Signed-off-by: Martin Åberg <martin.aberg@gaisler.com>
This adds support for the GRLIB APBUART UART peripheral commonly used in
LEON3/4/5 systems.
Driver features:
- Auto-detecting debug FIFO, if configured by GRMON
- Setting and getting UART transfer attributes
- Hardware FIFO if available
- Any number of APBUART devices based on devicetree
- Error status indication
- Polled operation
Signed-off-by: Martin Åberg <martin.aberg@gaisler.com>
