Enable serial interface on i.MX8ULP.
This also includes a SHA update for hal_nxp which
pulls in the following commits relevant to Zephyr:
* 3366f234ed47 build: hal_nxp: add TPM counter support
* 6544455fcf46 Compile in PXP driver if LVGL is set to use
PXP.
* 31463a848bcd devices: MIMX8UD7: add definition for
LPUART_RX_TX_IRQS
Signed-off-by: Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>
This commit enables pinctrl on i.MX8ULP. This includes:
1) Adding `pinctrl_soc.h` header file.
2) Adding DTS node for IOMUXC1, which is one of the
IPs responsible for managing the 8ULP pads.
3) Adding .dtsi with pin definitions. For now, only
the LPUART7 pads are added to this file because this
is going to be the only consummer for now.
4) Modifying the `pinctrl_imx.c` driver to work for 8ULP.
5) Enabling the `CONFIG_HAS_MCUX_IOMUXC`, which is a
dependency of `CONFIG_PINCTRL_IMX`.
Signed-off-by: Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>
The SOC name `imx8ulp` has been just a placeholder until
support for the SOC's ADSP (since this is the only core
that's supported in Zephyr) could be added to the NXP HAL.
Now that the support has been added, to make use of it, the
SOC name `imx8ulp` has to be changed to `mimx8ud7`. As such,
this commit does the following:
1) Introduces SOC part number configuration - needed
by some HAL headers.
2) Replaces all occurrences of `imx8ulp` (as the SOC
name) with `mimx8ud7`.
3) Enables `CONFIG_HAS_MCUX`.
4) Aligns all `CONFIG_SOC_` configurations with the
new SOC name.
5) Updates SOF hash. This is needed to fix build issues
caused by this name change. This is not done in a separate
commit to preserve bisectability.
Signed-off-by: Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>
2024-03-28 09:41:15 +00:00
Renamed from boards/nxp/imx8ulp_evk/imx8ulp_evk_imx8ulp_adsp.dts (Browse further)
