Commit graph

369 commits

Author SHA1 Message Date
Enjia Mai
8b97e7b29f soc: xtensa: split the cavs server and the FW loader
Spilt the cavs server and FW loader, to make the cavstool.py
a pure FW loader and runner as it used to be. The reasons is
try to keep the FW loader won't be affected by the client-
server-based HW service as possible, and more easy to debug.

After splitting them, the service program spawns another
process to run the FW loader. The advantage is no matter when
the FW loader is stuck, the service can detect and stop it,
then continue to next test.

Fixes #47652.

Signed-off-by: Enjia Mai <enjia.mai@intel.com>
2022-09-16 13:34:05 -04:00
Enjia Mai
581fc89084 soc: xtensa: tool: duplicate the cavstool.py to remote-fw-service.py
Copy cavstool.py to remote-fw-service.py in order to track changes
for following splitting work of cavstool.py.

Signed-off-by: Enjia Mai <enjia.mai@intel.com>
2022-09-16 13:34:05 -04:00
Lauren Murphy
85445474f2 boards, dts: fix filenames and dts refs for adsp clock
Changes filenames and DTS references from CAVS clock to
ADSP clock.

Signed-off-by: Lauren Murphy <lauren.murphy@intel.com>
2022-09-14 07:23:08 -04:00
Lauren Murphy
1983a4c50c boards, dts: fix namespace for intel adsp cavs, ace
Fixes namespace for Intel ADSP CAVS and ACE boards.

Signed-off-by: Lauren Murphy <lauren.murphy@intel.com>
2022-09-14 07:23:08 -04:00
Flavio Ceolin
b10c526352 ace: power: Only define d0i3 stack when needed
If the target is built without CONFIG_PM this stack is not
used and does not need to be defined.

Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
2022-09-13 08:45:34 -04:00
Kai Vehmanen
1a6d868400 soc: xtensa: tools: do not interfere with IPC in logs-only mode
The tool has caused some hard to detect failures when used
concurrently with the SOF Linux driver to observe logs. This
has been rootcaused to the code to handle and send IPC messages
that has been active even in logs-only mode. In vast majority
of cases, the SOF kernel driver is faster to act and handles
the IPC interrupts. But occasionally the cavstool.py timing was
just right and it managed to ack a message before Linux driver.

Fix the problem by not handling IPC messages when the tool
is run in logs-only mode.

Reported-by: Peter Ujfalusi <peter.ujfalusi@linux.intel.com>
Signed-off-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
2022-09-13 08:41:32 -04:00
Flavio Ceolin
d80be13791 intel_adsp: Use vectors offset defined in the hal
Do not hardcode vectors offset, instead get this values from the HAL.

Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
2022-09-09 16:53:12 -04:00
Flavio Ceolin
bfdd5a7517 intel_adsp: ace: Remove un-existent vectors
Interrupt vectors level 5 and 6 are not available in ACE. Just remove
them from the linker script.

Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
2022-09-09 16:53:12 -04:00
Flavio Ceolin
d103eee642 intel_adsp: ace: Fix debug vector address
In ace15_mtpm the debug exception vector address is mapped to INTLEVEL4
and not INTLEVEL 6. This can be checked in the core-isa header:

"""
define XCHAL_DEBUG_VECTOR_VADDR        XCHAL_INTLEVEL4_VECTOR_VADDR
"""

in
modules/hal/xtensa/zephyr/soc/intel_ace15_mtpm/xtensa/config/core-isa.h

Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
2022-09-09 16:53:12 -04:00
Flavio Ceolin
f37e7cdd3d intel_adsp: Do not use hal namespace
Do not define symbols using xtensa hal namespace.

Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
2022-09-09 16:53:12 -04:00
Flavio Ceolin
b5a0567984 intel_adsp: Rename common file
Symbols defined in cavs-vectors.h is also used by ace, just rename it
to avoid confusion.

Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
2022-09-09 16:53:12 -04:00
Flavio Ceolin
45465708f0 soc: intel_adsp: Add ACE soc series
ACE15_MTPM is one SOC from the ACE series. Organize
it following cavs pattern.

Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
2022-09-09 16:03:59 -04:00
Ederson de Souza
cf6bad78c4 soc/xtensa/intel_adsp: Disable L2 cache at boot based on Kconfig
Instead of deciding based on SoC version, add information to Kconfig and
get it from there on code.

Signed-off-by: Ederson de Souza <ederson.desouza@intel.com>
2022-09-08 18:03:33 -04:00
Ederson de Souza
fcdc9c78e2 soc/xtensa/intel_adsp: Get register address from DTS
Instead of hardcoding it where it's used.

Signed-off-by: Ederson de Souza <ederson.desouza@intel.com>
2022-09-08 18:03:33 -04:00
Ederson de Souza
5f4e2f99f0 soc/xtensa/intel_adsp/cavs: Init HP SRAM based on Kconfig
Instead of deciding to init based on SoC version, define that
information in Kconfig and use it from there.

Signed-off-by: Ederson de Souza <ederson.desouza@intel.com>
2022-09-08 18:03:33 -04:00
Ederson de Souza
9b7375d82a soc/xtensa/intel_adsp/common: Power on cache SRAM banks based on Kconfig
Instead of using SoC version to decide to power on or not, add this
information to Kconfig and get it from there.

Signed-off-by: Ederson de Souza <ederson.desouza@intel.com>
2022-09-08 18:03:33 -04:00
Ederson de Souza
c1dc2683b9 drivers/dai/intel/ssp: Get number of SSP ports from Kconfig
Instead of using SoC versions, define the information about base and
extended ports on Kconfig, and use this information from there.

Signed-off-by: Ederson de Souza <ederson.desouza@intel.com>
2022-09-08 18:03:33 -04:00
Ederson de Souza
79980f250c drivers/dai/intel/ssp: Decide about clock gating based on Kconfig
Instead of using version of the SoC, declare on Kconfig the need for it,
and use this information to decide upon enabling the code or not.

Signed-off-by: Ederson de Souza <ederson.desouza@intel.com>
2022-09-08 18:03:33 -04:00
Flavio Ceolin
9f13c1bf95 intel_adsp: ace: Fix wrong type assignment
error: assignment to 'void *' from 'unsigned int' makes pointer from int
|         lpsheader->lp_restore_vector = (uint32_t) &dsp_restore_vector;

Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
2022-09-08 17:54:35 -04:00
Flavio Ceolin
2851815c22 intel_adsp: ace: Add missing header on power.c
MEMCTL_L0IBUF_EN is defined in corebits.h

Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
2022-09-08 17:54:35 -04:00
Andy Ross
b141551cba arch/xtensa: Properly namespace special register API
The Xtensa arch has historically had state/user register accessor
macros with bare three-byte symbol names.  I think this might have
been in the original Cadence-contributed arch integration, but I'm not
sure.  In any case they also exist in the same names in vendor
HAL/toolchain code and are causing collisions.  We never should have
had these symbols exposed in our header.

Put them under an XTENSA_ prefix to decollide.

Signed-off-by: Andy Ross <andyross@google.com>
2022-09-07 20:28:06 -04:00
Andrey Borisovich
c75e6cfcb9 soc: intel_adsp_ace1x: Added IPC/IDC implementation
Added IPC and IDC implementation for Intel ADSP ACE1X SoCs.

Co-authored-by: Serhiy Katsyuba <serhiy.katsyuba@intel.com>
Signed-off-by: Andrey Borisovich <andrey.borisovich@intel.com>
2022-09-06 15:33:24 -04:00
Gerard Marull-Paretas
79e6b0e0f6 includes: prefer <zephyr/kernel.h> over <zephyr/zephyr.h>
As of today <zephyr/zephyr.h> is 100% equivalent to <zephyr/kernel.h>.
This patch proposes to then include <zephyr/kernel.h> instead of
<zephyr/zephyr.h> since it is more clear that you are including the
Kernel APIs and (probably) nothing else. <zephyr/zephyr.h> sounds like a
catch-all header that may be confusing. Most applications need to
include a bunch of other things to compile, e.g. driver headers or
subsystem headers like BT, logging, etc.

The idea of a catch-all header in Zephyr is probably not feasible
anyway. Reason is that Zephyr is not a library, like it could be for
example `libpython`. Zephyr provides many utilities nowadays: a kernel,
drivers, subsystems, etc and things will likely grow. A catch-all header
would be massive, difficult to keep up-to-date. It is also likely that
an application will only build a small subset. Note that subsystem-level
headers may use a catch-all approach to make things easier, though.

NOTE: This patch is **NOT** removing the header, just removing its usage
in-tree. I'd advocate for its deprecation (add a #warning on it), but I
understand many people will have concerns.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2022-09-05 16:31:47 +02:00
Andrey Borisovich
2e04bfdfe0 soc: intel_adsp: Refactored IPC/IDC
Changes to code:
1. Renamed CAVS_IPC API from common/include/cavs_ipc.h to
common/include/intel_adsp_ipc.h. Renamed all API functions and structs -
added "intel_adsp_" prefix.
2. Moved definitions from intel-ipc-regs.h and ace-ipc-regs.g to SOC
specific headers include/<soc_name>/adsp_ipc_regs.h.
3. Added new common intel_adsp_ipc_devtree.h header with new
macros to retrieve IPC and IDC nodes and register addresses.
Put those new macros in code replacing hardcoded values outside of
devicetree.
4. Changed documentation of IDC and renamed IDC register struct
to have common name between all intel adsp socs.
5. Removed excessive docs description on cAVS IPC protocol.

Changes to Devicetree:
1. Renamed in all CAVS boards .dtsi files content in IPC nodes:
   - "cavs_host_ipc" node labels to "adsp_ipc" labels.
   - compatible "intel,cavs-host-ipc" renamed to
     "intel,adsp-host-ipc".
2. Added (previously missing) yaml file for "intel,adsp-host-ipc"
   compatible.
3. Renamed in all CAVS boards .dtsi files content in IDC nodes:
   - "idc" node labels to "adsp_idc" labels.
   - compatible "intel,cavs-idc" renamed to "intel-adsp-idc"
4. Renamed intel,cavs_idc.yaml file to intel,adsp_idc.yaml
   so it is suitable for both CAVS and ACE SoC family.
   Moved it from ipm bindings to ipc bindings where it belongs.

Changes to Kconfig:
1. Renamed existing Kconfig option CONFIG_CAVS_IPC to
   INTEL_ADSP_IPC.
2. For renamed INTEL_ADSP_IPC addded default value based on
   status of the "adsp-ipc" and "adsp-ipc" node.

Signed-off-by: Andrey Borisovich <andrey.borisovich@intel.com>
2022-09-02 08:18:32 -04:00
Tomasz Leman
90a4e60893 intel: adsp: add restore vector after pg
This patch adds core restore vector. FW will restore core context from
memory and then return to the state it was in before power gaiting.

Adding struct of LPSRAM header. ROM during reboot check this struct in
serching for magic value and restore vector address.

Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
2022-09-02 10:53:52 +00:00
Tomasz Leman
9d9865d6cc intel: adsp: d0i3 initial implementation
This patch adds initial implementation of dynamic power gating for ace
platforms. The code is limited to enabling PG in HW registers and
disabling all interrupts.

CPU context storing and restoring still needs to be implemented. PG at
this moment will cause FW to halt during reboot.

Patch contains small refractor. Value CORE_POWER_CHECK_DELAY has been
moved to common header so it can be reused in other places.

Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
2022-09-02 10:53:52 +00:00
Tomasz Leman
98e95d1d68 intel: adsp: power down procedure rename
This patch is renaming primary core power down procedure by removing ACE
prefix. Prefix was added to avoid name conflicts while linking. The
problem is now resolved and name can be revert to the original version.

Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
2022-09-02 10:53:52 +00:00
Ederson de Souza
a7e9166574 soc/xtensa/intel_adsp/cavs: Fix XTENSA_CCOUNT_HZ value
The default value is actually 400MHz on cavs15 and cavs18.

Fixes: #49711

Signed-off-by: Ederson de Souza <ederson.desouza@intel.com>
2022-09-01 10:25:45 +02:00
Anas Nashif
4f81568286 intel_adsp: cavs: move CAVS linker script to series
This linker script is CAVS specific, so move it out of common/ and make
it part of the CAVS series.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2022-08-29 16:27:51 -04:00
Anas Nashif
f3729445e3 intel_adsp: cavs: push all common kconfigs into series
Consolidate common kconfigs of the CAVS series into the series level and
remove duplication among all supported SoCs.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2022-08-29 16:27:51 -04:00
Kai Vehmanen
8195ea7ea0 logging: Intel ADSP mtrace logging backend
Implements a logging backend implementing the mtrace protocol
to relay log messages over SRAM. This protocol is implemented
by the SOF Linux driver ("mtrace" debugfs interface).

This implementation follows example of the ADSP HDA logger implemented
in commit 6913da9ddd ("logging: cAVS HDA based logger").

Cc: Tom Burdick <thomas.burdick@intel.com>
Signed-off-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
2022-08-29 10:43:42 +02:00
Kai Vehmanen
45c82c9090 arch/xtensa: adsp: add SRAM window 2 initialization
Define SRAM window 2 details to the headers and open access to host to
the window in bootloader.

Also clarify Kconfig documentation that the semantics of the windows can
vary depending on which host<->DSP communication scheme is in use.

Signed-off-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
2022-08-29 10:43:42 +02:00
Tom Burdick
3a4864bdd2 logging: adsp hda backend improvements
* Adds a default hook and init function for cavstool.
* Adds an optional padding on flush feature to ensure all data is written.
* Fixes an error in cavstool.py for correctly wrapping the ring buffer.
* The test case now ensures wraps and flushes occur numerous times.

Signed-off-by: Tom Burdick <thomas.burdick@intel.com>
2022-08-26 21:33:10 -04:00
Anas Nashif
6c7bf09222 intel_adsp: fix leakage of Kconfigs in soc family defconfig
Add missing conditionals and move CAVS related configs into own series
defconfig.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2022-08-26 13:17:02 -04:00
Anas Nashif
a04d06514a Revert "intel_adsp: cavs: irq: simplify code"
This reverts commit 2241fb0592.

Fixes #49200

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2022-08-23 20:46:10 -04:00
Flavio Ceolin
96e988c53a intel_adsp: Do not use xtensa hal with xcc-clang
Do not usu XTENSA_HAL when building with xt-clang, instead uses
the HAL provided together with the toolchain. Just like it is
done with "xcc" toolchain variant.

Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
2022-08-23 10:13:43 +02:00
Gerard Marull-Paretas
a202341958 devices: constify device pointers initialized at compile time
Many device pointers are initialized at compile and never changed. This
means that the device pointer can be constified (immutable).

Automated using:

```
perl -i -pe 's/const struct device \*(?!const)(.*)= DEVICE/const struct
device *const $1= DEVICE/g' **/*.c
```

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2022-08-22 17:08:26 +02:00
Tom Burdick
efc0928570 dma/hda: Use the correct register block size for each IP block
Previous versions were using, incorrectly, the host in/out regblock size
of 40 bytes for all peripherals when in fact the link in/out regblock size
is 20 bytes in size.

Signed-off-by: Tom Burdick <thomas.burdick@intel.com>
2022-08-18 14:54:57 -05:00
Enjia Mai
5b5107090d soc: xtensa: tools: add specifying log and request port for cavs client
Besides in a form of {host}:{port} to specifying the port using, we
also support specifying --log-port and --req-port parameters for the
cavstool client.

Signed-off-by: Enjia Mai <enjia.mai@intel.com>
2022-08-16 22:51:53 -07:00
Enjia Mai
a38f533278 soc: xtensa: tools: remove dependency of netifaces package
Because we use INADDR_ANY by default now, specifying a net interface
is no longer needed. Remove it and remove the dependency of the
netifaces python package.

Fixes. #48584

Signed-off-by: Enjia Mai <enjia.mai@intel.com>
2022-08-16 22:51:53 -07:00
Enjia Mai
6a6a8a9fde soc: xtensa: cavstool server support specifying the port and iface
Make the cavstool service can start with specifying the port
optionally by:

   cavstool.py -s {host}:{log port} --req-port {req port}
OR
   cavstool.py -s {host} --log-port {log port} --req-port {req port}

And we can also specify the network interface instead:

   cavstool.py -i {network iface}

If the server address or the network interface is not specified,
it will use INADDR_ANY by default.

Signed-off-by: Enjia Mai <enjia.mai@intel.com>
2022-08-16 22:51:53 -07:00
Enjia Mai
e33fd73546 soc: xtensa: add support for specifying the service port
Add specifying the port for the remote cavstool remote service.
Ex.

    west flash --remote-host {host}:{port} \
               --pty {host}:{port}

Specify the port is optional when running west.

And another major change is now we have to specify the remote log
service by --pty to make it output the log message immediately.
Previously it will output directly. Why we make this change is
because this is more close to the behavior we use west flash.

Fixes. #46865

Signed-off-by: Enjia Mai <enjia.mai@intel.com>
2022-08-16 22:51:53 -07:00
Flavio Ceolin
b39d897b09 adsp: gpdma: Move gpdma code to driver
DMA controller ownership can be done in the driver
initialization, it does not need to be part of the SoC. It simplify
the code and remove duplicated definitions.

Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
2022-08-15 08:21:53 +00:00
Anas Nashif
61103d415a intel_adsp: clk: add braces around if/for
add missing curly braces around if/for statements.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2022-08-12 08:08:32 -04:00
Anas Nashif
2241fb0592 intel_adsp: cavs: irq: simplify code
Put duplicate snippet to get the device into a function.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2022-08-10 14:30:45 -04:00
Anas Nashif
1df711dea9 intel_adsp: remove unused defines IOAPIC_*
Those IOAPIC defines do not belong here..

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2022-08-10 14:30:45 -04:00
Anas Nashif
b1074152b0 intel_adsp: move z_soc_irq_* declarations
Move prototype declaration to include/zephyr/arch/xtensa/irq.h.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2022-08-10 14:30:45 -04:00
Anas Nashif
be2b943cfb intel_adsp: move cavs irq code under cavs/
This code is not common and is CAVS specific, so move it under cavs/
series.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2022-08-10 14:30:45 -04:00
Anas Nashif
9feaced96f intel_adsp: move power initialization to a common place
Make all series consistent with regard to where code is located and put
the power init code in power.c alongside other power related code.
Reduce soc.c per series to an empty file that can be removed.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2022-08-10 14:30:45 -04:00
Anas Nashif
fc97a71c4d intel_adsp: use one soc_init for all series
initializing the SoC is the same across series, so put everything in one
place in the common code base.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2022-08-10 14:30:45 -04:00