irq_enable() should be called with the composite IRQ code as its
argument, not just the Xtensa proper part of it.
Signed-off-by: Guennadi Liakhovetski <guennadi.liakhovetski@linux.intel.com>
BT support requires lots of PROVIDE calls that cannot
be added into this linker file. All necessary includes
were moved into hal module to proper handled as needed.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
When BT and WiFi coexists, IRAM usage increases a lot.
Add configuration that allow wifi symbols
to be placed in flash, freeing space in IRAM.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
xthal_window_spill call has to be placed into IRAM
in order to allow flash cache disabled operation, otherwise
it will crash.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
The sentry symbols that mark the ends of the newlib heap area were
being placed in cached memory, which violates the coherence rules.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
Turns out that the user can configure the "zephyr.elf" name via
kconfig to be "something_else.elf" instead. And there's a test the
does this. Use the right variable; don't hardcode.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
This was added early when we had (somewhat oddly) a log subsystem
backend but not a printk char_out hook. Now we have one backend that
works with both. No need, and this fixes build errors with a handful
of tests that specify LOG_MINIMAL (LOG_PRINTK requires the full log
subsystem and doesn't work with MINIMAL).
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
In commit efa05d1e42da ("soc/intel_adsp: Put initial stack into the
CPU0 interrupt stack") the "_end" symbol was accidentally removed from
the linker script. Newlib needs this to size its heap.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
The Xtensa L1 cache layer has straightforward semantics accessible via
single-instructions that operate on cache lines via physical
addresses. These are very amenable to inlining.
Unfortunately the Xtensa HAL layer requires function calls to do this,
leading to significant code waste at the calling site, an extra frame
on the stack and needless runtime instructions for situations where
the call is over a constant region that could elide the loop. This is
made even worse because the HAL library is not built with
-ffunction-sections, so pulling in even one of these tiny cache
functions has the effect of importing a 1500-byte object file into the
link!
Add our own tiny cache layer to include/arch/xtensa/cache.h and use
that instead.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
Instead of passing the crt1 _start function as the entry code for
auxiliary CPUs, use a tiny assembly stub instead which can avoid the
runtime testing needed to skip the work in _start. All the crt1 code
was doing was clearing BSS (which must not happen on a second CPU) and
setting the stack pointer (which is wrong on the second CPU).
This allows us to clean out the SMP code in crt1.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
Zephyr's normal architecture is to do all initialization in the
interrupt stacks. The CAVS code was traditionally written to start
the stack at the end of HP-SRAM, where it has no protection against
overlap with other uses (e.g. MP startup used the same region for
stacks and saw cache collisions, and the SOF heap lives in this area
too). Put it where Zephyr expects and we'll have fewer surprises.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
The kernel passes the CPU's interrupt stack expected that it will
start on that, so do it. Pass the initial stack pointer from the SOC
layer in the variable "z_mp_stack_top" and set it in the assembly
startup before calling z_mp_entry().
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
There's no need to muck with the cache directly as long as we're
careful about addressing the shared start record through an uncached
volatile pointer.
Correct a theoretical bug with the initial cache invalidate on the
second CPU which was actually doing a flush (and thus potentially
pushing things the boot ROM wrote into RAM now owned by the OS).
Optimize memory layout a bit when using KERNEL_COHERENCE; we don't
need a full cache line for the start record there as it's already in
uncached memory.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
The multiprocessor entry code here had some bits that look to have
been copied from esp32, including a clumsy stack switch that's needed
there. But it wasn't actually switching the stack at all, which on
this device is pointed at the top of HP-SRAM and can stay there until
the second CPU swaps away into a real thread (this will need to change
once we support >2 CPUS though).
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
The trace output layer was using this transformation already, make it
an official API. There are other places doing similar logic that can
benefit.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
There was a bunch of dead historical cruft floating around in the
arch/xtensa tree, left over from older code versions. It's time to do
a cleanup pass. This is entirely refactoring and size optimization,
no behavior changes on any in-tree devices should be present.
Among the more notable changes:
+ xtensa_context.h offered an elaborate API to deal with a stack frame
and context layout that we no longer use.
+ xtensa_rtos.h was entirely dead code
+ xtensa_timer.h was a parallel abstraction layer implementing in the
architecture layer what we're already doing in our timer driver.
+ The architecture thread structs (_callee_saved and _thread_arch)
aren't used by current code, and had dead fields that were removed.
Unfortunately for standards compliance and C++ compatibility it's
not possible to leave an empty struct here, so they have a single
byte field.
+ xtensa_api.h was really just some interrupt management inlines used
by irq.h, so fold that code into the outer header.
+ Remove the stale assembly offsets. This architecture doesn't use
that facility.
All told, more than a thousand lines have been removed. Not bad.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
Only the CAVS 1.5 linker script has full support for the coherence
features, don't advertise it on the other SoC's yet.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
This change moves .rodata for panic handler and fatal.c into DRAM
Moves panic handler and its dependent functions into IRAM
Signed-off-by: Shubham Kulkarni <shubham.kulkarni@espressif.com>
Fix kernel.common and kernel.common test cases fail due to build error
in platform intel_adsp_cavs15, 18, 20, 25.
Signed-off-by: Enjia Mai <enjiax.mai@intel.com>
Currently Zephyr links reset-vector.S twice in xtensa builds:
into the bootloader and the main image. It is run at the end
of the boot loader execution and immediately after that again
in the beginning of the main code. This patch adds a
configuration option to select whether to link the file to the
bootloader or to the application. The default is to the
application, as needed e.g. for QEMU, SOF links it to the
bootloader like in native builds.
Signed-off-by: Guennadi Liakhovetski <guennadi.liakhovetski@linux.intel.com>
Disable RTC WDT enabled (by default) by 2nd stage bootloader in ESP-IDF.
This WDT timer ensures correct hand-over and startup sequence from
bootloader to application.
Enabling bootloader caused system clock initialization to fail
when clock rate is greater then 80MHz. This also fixes
esp32 clock source code.
Signed-off-by: Mahavir Jain <mahavir@espressif.com>
Looks like those two SoCs still had old header information depending on
Kconfig from SOF, remove those and set trace size directly.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
LPRAM_BASE and LPRAM_SIZE are duplicates of LP_SRAM_BASE and
LP_SRAM_SIZE respectively. Remove them and use LP_SRAM_*
consistently everywhere.
Signed-off-by: Guennadi Liakhovetski <guennadi.liakhovetski@linux.intel.com>
On cAVS 1.8, 2.0 and 2.5 LSPGISTS and LSPGCTL are located in a
different shim register range, they cannot be accessed, using the
usual SHIM_BASE offset.
Signed-off-by: Guennadi Liakhovetski <guennadi.liakhovetski@linux.intel.com>
CONFIG_BOOTLOADER_MCUBOOT is never used in cAVS builds, remove
code, supposedly supporting it.
Signed-off-by: Guennadi Liakhovetski <guennadi.liakhovetski@linux.intel.com>
shim.h on cAVS 2.5 contains register definitions, copy-pasted
from other architectures. Fix them to correct values.
Signed-off-by: Guennadi Liakhovetski <guennadi.liakhovetski@linux.intel.com>
Tigerlake H has less RAM and fewer cores. Both should be
supported, selectable at the board level. For now use the H
configuration as more readily available for testing.
Signed-off-by: Guennadi Liakhovetski <guennadi.liakhovetski@linux.intel.com>
A configuration with CONFIG_MP_NUM_CPUS > 1 and CONFIG_IPM_CAVS_IDC not
defined is valid if COMFIG_SMP is disabled.
Signed-off-by: Guennadi Liakhovetski <guennadi.liakhovetski@linux.intel.com>
