This commit introduces a driver for ADC keys, a common circuit design where
keys are connected to an ADC input via a resistor ladder.
Signed-off-by: Chen Xingyu <hi@xingrz.me>
Added a simple driver for RRAM. It is implemented as a flash driver,
because the "RRAM eFlash" macro obeys flash-like constraints.
Although users are not required to erase before write.
Signed-off-by: Jakub Zymelka <jakub.zymelka@nordicsemi.no>
Add driver for ScioSense ENS160 multi-gas sensor. The driver includes
support for I2C and SPI, attributes for setting temperature and
humidity compensation and data ready trigger.
Also add ScioSense to the list of vendor prefixes.
Signed-off-by: Gustavo Silva <gustavograzs@gmail.com>
Add clarifications to mipi-dbi bindings to avoid the confusion
between two options, write-only and duplex.
Signed-off-by: Eve Redero <eve.redero@gmail.com>
Change reset pin polarity for MIPI DBI SPI controller, so that the board
devicetree is responsible for setting the GPIO to active low, and the
driver always sets the pin to a logic 1 to reset the display.
Fixes#68562
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Display is not working on STM32F429i-DISC1 board because
display_blanking_off() needs to be sent to ILI9341 device, but it's sent
to LTDC instead which does not implement it.
This patch adds a LTDC DT property that provides the pHandle of the
display's own controller so that display_blanking_off/on are forwarded to
it when they are called by an application.
Signed-off-by: Abderrahmane Jarmouni <abderrahmane.jarmouni-ext@st.com>
Add a set of bindings that will be used in the nRF54H20 SoC definition.
Extend the existing GPIOTE binding with properties needed for this SoC.
Also do a tiny clean-up in the bindings added recently for nRF54L15
(HFXO and LFXO).
Signed-off-by: Grzegorz Swiderski <grzegorz.swiderski@nordicsemi.no>
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
This adds new NXP mailbox driver for MBOX device.
NXP mailbox IP driver supports sending data between cores.
It uses 32 bit register to trigger irq to other core.
This driver implementation uses 4 bits for channel selection of
triggering mode, 4 bits for channel selection of data transfer and
rest 24 bits for data.
NXP mailbox IP Reference Manual UM11126, Chapter 52.
https://www.nxp.com/webapp/Download?colCode=UM11126
Signed-off-by: Tomas Galbicka <tomas.galbicka@nxp.com>
Address and size are given by the DTS register property
of the qspi nor. The size Property becomes useless.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Address and size are given by the DTS register property
of the ospi nor. The size Property becomes useless
Signed-off-by: Francois Ramu <francois.ramu@st.com>
1. Configure 'core-clock' to 192MHz to generate necessary 48MHz
2. Support workaround to disallowing ISO IN/OUT EPs to be assigned
the same EP numbers
Signed-off-by: Chun-Chieh Li <ccli8@nuvoton.com>
drivers: eth: phy: tja1103: Handle link change
These changes enable -
TJA1103 driver to gracefully handle Link connect or disconnect events
between Ethernet PHY and its link partner and notify it to the
upper network layers
Signed-off-by: Sumit Batra <sumit.batra@nxp.com>
This adds support for the GRLIB SPIMCTRL SPI controller used in LEON and
NOEL-V systems. SPIMCTRL can operate in two different modes: In the
default mode it allows memory-mapped read access to the flash data. When
set in the user mode, it can be used to generate SPI bus transactions.
Signed-off-by: Martin Åberg <martin.aberg@gaisler.com>
Convert ili9xxx display drivers to use MIPI DBI API. Due to the fact
this change requires a new devicetree structure for the display driver
to build, required devicetree changes are also included in this commit
for all boards and shields defining an instance of an ili9xxx display.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
SPI controllers can easily implement MIPI DBI mode C, with the help of
GPIO pins for the reset and command/data signals. Introduce a MIPI DBI
compliant SPI driver, which emulates MIPI DBI mode C (SPI 3 and 4 wire).
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Introduce MIPI DBI driver class. MIPI DBI devices encompass several
interface types. All interfaces have a data/command, reset, chip select,
and tearing effect signal
Beyond this, MIPI DBI operates in 3 modes:
Mode A- 16/8 data pins, one clock pin, one read/write pin. Similar to
Motorola type 6800 bus
Mode B- 16/8 data pins, one read/write pin. Similar to Intel 8080 bus
Mode C- 1 data output pin, 1 data input pin, one clock pin.
Implementable using SPI peripheral, or MIPI-DBI specific controller.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
The LIS2DE12 is an ultra-low-power high- performance three-axis
linear accelerometer belonging to the “femto” family with digital
I2C/SPI serial interface standard output.
This driver is based on stmemsc HAL i/f v2.3
https://www.st.com/en/datasheet/lis2de12.pdf
Signed-off-by: Armando Visconti <armando.visconti@st.com>
Add a new #nordic,ficr-cells property, so that we can specify a FICR
offset in a phandle-array, e.g.
nordic,ficrs = <&ficr 0xff>;
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
This commit adds the `efinix,vexriscv-sapphire` compatible string. This
helps identify the core type from the final devicetree alone.
The VexRiscv core configuration is specific to the Efinix Sapphire SoC.
Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
This commits adds two new compatible strings:
* `openisa,ri5cy`
* `openisa,zero-ri5cy`
Adding these two new compats help identify the specific core defined by the
cpu node from the devicetree alone.
Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
This commit adds the `andestech,andescore-v5` compatible string. This helps
identify the core tpye form the final devicetree alone.
Andes doesn't define which core type from the v5 series the AE350 SoC uses,
so we're using the whole series name here.
Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
The OpenTitan Earlgrey SoC has the lowRISC Ibex CPU core. This commits adds
the `lowrisc,ibex` compatible string to reflect that.
Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
This commit adds the `litex,vexriscv-standard` compatible string. This
helps identify the core type from the final devicetree alone.
The VexRiscv core version is defined in this repository:
https://github.com/litex-hub/zephyr-on-litex-vexriscv.
Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
This commit moves the bindings of RISC-V cores from `dts/bindings/riscv` to
`dts/bindings/cpu`. This change aligns the bindings of RISC-V cores with
other architectures.
Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
Utilize a code spell-checking tool to scan for and correct spelling errors
in all files within the dts/bindings/adc and arm.
Signed-off-by: Pisit Sawangvonganan <pisit@ndrsolution.com>
Utilize a code spell-checking tool to scan for and correct spelling errors
in all files within the dts/bindings/bluetooth, can, dac and display.
Signed-off-by: Pisit Sawangvonganan <pisit@ndrsolution.com>
Utilize a code spell-checking tool to scan for and correct spelling errors
in all files within the dts/bindings/ethernet, gpio, i2c and
interrupt-controller.
Signed-off-by: Pisit Sawangvonganan <pisit@ndrsolution.com>
Utilize a code spell-checking tool to scan for and correct spelling errors
in all files within the dts/bindings/net, power-domain, pwm and qspi.
Signed-off-by: Pisit Sawangvonganan <pisit@ndrsolution.com>
Utilize a code spell-checking tool to scan for and correct spelling errors
in all files within the dts/bindings/retained_mem, rng, serial and spi.
Signed-off-by: Pisit Sawangvonganan <pisit@ndrsolution.com>
Utilize a code spell-checking tool to scan for and correct spelling errors
in all files within the dts/bindings/timer, usb-c, usb and watchdog.
Signed-off-by: Pisit Sawangvonganan <pisit@ndrsolution.com>
Utilize a code spell-checking tool to scan for and correct spelling errors
in all files within the dts/bindings/pinctrl directory.
Signed-off-by: Pisit Sawangvonganan <pisit@ndrsolution.com>
Utilize a code spell-checking tool to scan for and correct spelling errors
in all files within the dts/bindings/dma directory.
Signed-off-by: Pisit Sawangvonganan <pisit@ndrsolution.com>
