Commit graph

113820 commits

Author SHA1 Message Date
Chaitanya Tata
9b68218e9a net: l2: wifi: Make build time certs as optional
Certificates usage depends on STA/AP mode, but we don't have that
information at a build time, so, make all certs as optional and if a
file isn't found then generate an empty header so that corresponding C
code will be built.

Any missing mandatory certificates will be validated before connection
and connection is failed.

Signed-off-by: Chaitanya Tata <Chaitanya.Tata@nordicsemi.no>
2025-04-17 17:22:58 +02:00
Chaitanya Tata
c2f4e67c8a net: lib: tls_credentials_shell: Fix crash during delete
Deletion of credential should use the pointer from the reference slot
not the temporary buffer, this causes a crash (unknown error).

Signed-off-by: Chaitanya Tata <Chaitanya.Tata@nordicsemi.no>
2025-04-17 17:22:58 +02:00
Chaitanya Tata
31913efcbf snippets: wifi-enterprise: Add support for TLS credentials
Enable TLS credentials shell to manager Wi-Fi enterprise certs.

Signed-off-by: Chaitanya Tata <Chaitanya.Tata@nordicsemi.no>
2025-04-17 17:22:58 +02:00
Chaitanya Tata
d7b3bcd982 wifi: Move Wi-Fi enterprise configs to a snippet
Instead of having an overlay move the Enterprise configurations to a
dedicated snippet so that it can be enabled with any sample.

Can be used along with Wi-Fi snippet e.g., `-S
"wifi-ipv4;wifi-enterprise"`.

Signed-off-by: Chaitanya Tata <Chaitanya.Tata@nordicsemi.no>
2025-04-17 17:22:58 +02:00
Chaitanya Tata
7ba5e43cf5 net: lib: tls_credentials_shell: Add a config for heap
The volatile backend stores the credentials on the heap, so, explicitly
add a config option that can be overridden in case there are more certs
than the default.

Signed-off-by: Chaitanya Tata <Chaitanya.Tata@nordicsemi.no>
2025-04-17 17:22:58 +02:00
Chaitanya Tata
b2e7d7fc0c net: l2: wifi: Add support for run-time certificates
Using TLS credentials library add support for run-time certificates where
the installed certs are retrieved from the credential store (as of now
only volatile backend is tested).

This helps in production environments.

Implements #79564.

Signed-off-by: Chaitanya Tata <Chaitanya.Tata@nordicsemi.no>
2025-04-17 17:22:58 +02:00
Maochen Wang
90cd350c5a drivers: serial: fix console hang when waken up from PM3
The console can't input when waken up from PM3, as get the wrong
usart_intenset when process PM_DEVICE_ACTION_TURN_ON and the
USART interrupt is not enabled. Only saving usart_intenset after
PM action of PM_DEVICE_ACTION_TURN_OFF can fix this issue.

Signed-off-by: Maochen Wang <maochen.wang@nxp.com>
2025-04-17 09:06:38 +02:00
Tim Lin
db4344b06b drivers/i2c: ite: Use i2c_bitbang API for bus recovery
Replace the manually implemented GPIO-based I2C recovery logic
with Zephyr's i2c_bitbang API.

Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
2025-04-17 09:06:29 +02:00
Hao Luo
6f4b92d64d soc: ambiq: Optimize the inclusion relationship of header files
Optimized the inclusion relationship of header files

Signed-off-by: Hao Luo <hluo@ambiq.com>
2025-04-17 09:06:18 +02:00
Jun Lin
3f59fa36f1 soc: npcx: update the NUM_IRQS value for npcx4
The npcx4 SoC only uses 86 NVIC IRQ numbers.
This commit updates the number from 128 to 86 to reduce the memory
usage.

Signed-off-by: Jun Lin <CHLin56@nuvoton.com>
2025-04-17 09:06:07 +02:00
Daniel Hajjar
69713f4e6a posix: net: Fix undefined behavior
The signedness of the variable caused undefined behavior because the
sign bit is modified when it gets left-shifted.

This fixes that by changing it to an unsigned variable.

Signed-off-by: Daniel Hajjar <daniel.hajjar16@gmail.com>
2025-04-17 09:05:56 +02:00
Ryan McClelland
2c66a2adc0 drivers: i3c: add i3c controller and target kconfigs
I3C can contain a lot of features that may be unused. Add Kconfigs for
enabling controller and/or target code. Choosing just one can reduce
the code size footprint.

Signed-off-by: Ryan McClelland <ryanmcclelland@meta.com>
2025-04-17 09:05:36 +02:00
Aditya Bhutada
4102010456 drivers: espi: Add return value to eSPI send_vwire API
Added note about return value to the eSPI send_vwire API in the header:
-ETIMEDOUT & _EINVAL.

Signed-off-by: Aditya Bhutada <aditya.bhutada@intel.com>
2025-04-17 00:57:28 +02:00
Aditya Bhutada
2c36616dd2 drivers: espi: espi_mchp_xec: Fix the VW change check time
Adjusted the VW change check timings:
- Polling time changed from 100 uSec to 1 uSec.
- Timeout value changed from 10 mSec to 1 mSec.

This is to achieve the lowest possible pulse width for SCI VW in S0,
while ensuring that the VW change check is still reliable for S0iX
where SoC may take longer to process upstream events.

Also added -ETIMEDOUT error when failure.

Signed-off-by: Aditya Bhutada <aditya.bhutada@intel.com>
2025-04-17 00:57:28 +02:00
Daniel Leung
9cadc8cbec xtensa: userspace: use ADDX4 to calculate syscall table index
When looking for jump address in the syscall table, we need to
multiply the syscall ID by 4 before adding the address offset
of the beginning of the table. This is due to the jump address
being 32-bit (4 bytes). Instead of using two instructions to
shift the ID by 4 first and then the addition, we can use one
ADDX4 instruction to achieve the same result.

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2025-04-17 00:57:19 +02:00
Daniel Leung
277fa9e8ac xtensa: userspace: swap page tables via assembly code
Since the necessary register values are now pre-computed and
stored in the memory domain struct, we can use them directly
in various assembly locations, thus replacing the function
call to xtensa_swap_update_page_tables().

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2025-04-17 00:57:19 +02:00
Daniel Leung
689e1121cf kernel: typedef k_mem_domain_t and _mem_domain_info_t
Create alias for struct k_mem_domain into k_mem_domain_t,
and struct _mem_domain_info into _mem_domain_info_t via
typedef. These are needed to generate offsets via
GEN_OFFSET_SYM.

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2025-04-17 00:57:19 +02:00
Daniel Leung
2abf7ce2f1 xtensa: userspace: prevent potential privilege escalation
When context switching and dealing with non-nested interrupts,
the context to be restored are saved in the thread stack.
When userspace is enabled, this means saving context into
the user stacks for user threads. This allows PS values to be
manipulated externally by setting PS.RING in the saved PS
value to 0, resulting in granting kernel access privilege when
the thread is restored. To prevent this, we store the PS value
into the thread struct instead, where user threads cannot
manipulate that. Note that nested interrupts and syscalls are
not using the user stack but the interrupt stack and thread
privileged stack respectively, where they are not accessible
under user mode.

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2025-04-17 00:57:19 +02:00
Daniel Leung
d5c2e4b03c xtensa: userspace: workaround return PC calc with loops
When syscall assembly is executed, the EPC points to the syscall
instruction, and we have to manually advance it so we will
return to the instruction after syscall to continue execution.
However, with zero-overhead loops and the syscall instruction is
the last instruction, this simple addition does not work as it
would point past the loop and would have skipped the loop.
Because of this, syscall entrance would need to look at the loop
registers and set the PC back to the beginning of loop if we are
still looping. Assuming most of the syscalls are not inside
loops, the extra handling code consumes quite a few cycles.
To workaround this, simply adds a nop after syscall so we no
longer have to deal with loops at syscall entrance, and that
a nop is faster than all the code to manipulate loop registers.

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2025-04-17 00:57:19 +02:00
Daniel Leung
bdb5723f28 xtensa: userspace: remove ununsed syscall helpers
Syscall helpers with 0, 1, 2, and 3 number of args are not
used so remove them.

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2025-04-17 00:57:19 +02:00
Daniel Leung
b0693ee41b xtensa: userspace: handle privileged stack in arch_cohere_stacks
This extends arch_cohere_stacks() to handle privileged stacks of
user threads when userspace is enabled.

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2025-04-17 00:57:19 +02:00
Daniel Leung
9ebe16b6e7 xtensa: no need to restore A0/A1 if not coherence in irq exit
Towards the end of interrupt handling, and before restoring
context, we would spill all register windows. This requires
A0 and A1 to be restored from the saved context so spilling
would work correct. However, when coherence is enabled,
window spilling has already been done earlier so there is
no need to spill the register windows again. So there is
no need to restore A0 and A1. They will be restored again
before returning from interrupt anyway.

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2025-04-17 00:57:19 +02:00
Daniel Leung
0dce0bdc0b xtensa: userspace: pre-compute MMU registers at domain init
Instead of computing all the needed register values when
swapping page tables, we can pre-compute those values when
the memory domain is first initialized. Should save some
time during context switching.

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2025-04-17 00:57:19 +02:00
Daniel Leung
36064939d3 xtensa: no need for flush register if threads are pin only
There is no need for ZSR_FLUSH when threads are pin only
(CONFIG_SCHED_CPU_MASK_PIN_ONLY=y), so there is no need to
reserve it.

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2025-04-17 00:57:19 +02:00
Daniel Leung
50abe89970 xtensa: userspace: use ZSR_RFI_LEVEL for userspace enter
In xtensa_userspace_enter, we were hard-coding to use level 2
interrupt return mechanism to pivot to user mode and start
running the user thread. However, EPC2 and EPS2 may be used
for other purposes, and they could be used for interrupt
return if there are only two level interrupts. So change
the userspace enter to use ZSR_RFI_LEVEL, ZSR_EPC and ZSR_EPS
instead to be more explicit.

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2025-04-17 00:57:19 +02:00
Daniel Leung
af5dfff3ae xtensa: userspace: use ZSR_RFI_LEVEL for syscall return
When returning from syscall, we cannot use RFE by using EPC1.
As there is no EPS1, we would need to write to PS before
returning. However, this creates a situation where interrupts
are being enabled (since PS is set), and any interrupts will
overwrite EPC1 before we return (which ensures chaos as we
would be returning to the wrong address). So utilize the same
mechanism as interrupt returning by use ZSR_EPS, ZSR_EPC and
ZSR_RFI_LEVEL.

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2025-04-17 00:57:19 +02:00
Daniel Leung
514cd38431 xtensa: userspace: remove jump to _syscall_returned
There is no need to do a jump to _syscall_returned as it is
the next to be run anyway. Keep the label there so we can
set breakpoint if needed.

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2025-04-17 00:57:19 +02:00
Daniel Leung
7f028e2f6e xtensa: userspace: align stack before calling syscall handler
We stuff the 7th argument into stack by moving the stack pointer
before calling syscall handler. The Xtensa ABI says stack must
be 16-byte aligned. So instead of moving stack pointer 4 bytes,
we move 16 bytes (assuming stack has been aligned so far).

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2025-04-17 00:57:19 +02:00
Daniel Leung
482f9fbbfb xtensa: pad IRQ stack frame to be 16 bytes aligned
Xtensa ISA mentions that stack always needs to be aligned on
16 bytes. So we need to pad the stack frame to be also 16 bytes
aligned when dealing with interrupts. Or else the stack would
not be 16 bytes aligned when we add the stack frame to stack
during interrupt handling.

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2025-04-17 00:57:19 +02:00
Daniel Leung
7229b00433 xtensa: window may overflow during irq stack crossing
When crossing stack during interrupt handling, we do two call4
to pivot to the interrupt stack, with arguments to these two
call4 stashed in A6, A10 and A11. However, A4-A11 may be marked
as invalid in the register file, and accessing them would
result in window overflowing. At that point, A0 and A1 are not
setup to handle window overflows, and will result in registers
being stashed in incorrect location, resulting in incorrect
value being restored during window underflowing. So move around
the code a bit to restore A0 and A1 properly before accessing
A4-A11.

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2025-04-17 00:57:19 +02:00
Daniel Leung
9610f1a229 xtensa: mmu: do not force small vector table
Do not force CONFIG_XTENSA_SMALL_VECTOR_TABLE_ENTRY when MMU
is enabled. It is up to the SoC to decide whether they need
this.

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2025-04-17 00:57:19 +02:00
Daniel Leung
774b73c8a4 xtensa: userspace: swap page table at end of cross stack call
The logic to swap page tables or MPU entries is moved to the end
of cross stack call, since it is still running in the interrupt
stack instead of the thread stack. The old logic was calling
the swap functions in the outgoing thread stack, which is not
desirable.

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2025-04-17 00:57:19 +02:00
Daniel Leung
e0752c2938 xtensa: userspace: swap page table earlier in xtensa_switch
When switching page table and MPU enties, we need to call
corresponding functions via call4 which would move the register
window. So we need to do that earlier before we start saving
context into stack by manipulating stack pointer manually which
definitely would interfere with window spilling.

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2025-04-17 00:57:19 +02:00
Daniel Leung
6874cdcf19 xtensa: fix unneeded cache invalidation in arch_cohere_stacks()
During arch_cohere_stacks(), the used portion of the outgoing
thread is cache flushed, and then the unused portion of cache
invalidated. However, this results in the cache line at
the stack pointer being flushed and then invalidated due to
how sys_cache_data_*() operates. If we are swapping back to
the same thread (e.g. after handling interrupt), this cache
line will need to be retrieved again from main memory since
it has already been invalidated. This creates unnecessary
data move between cache and main memory. So create our own
version of cache flushing and invalidation routines just for
arch_cohere_stacks(). Bouns is that these work directly with
bounding addresses and skips the size calculation which should
save a little bit amount of execution time.

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2025-04-17 00:57:19 +02:00
Daniel Leung
9fb87cf586 xtensa: remove second cross stack trampoline
This removes _xstack_call1_* trampoline as we can simply use
callx4 to jump to the interrupt handler.

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2025-04-17 00:57:19 +02:00
Daniel Leung
3f8e4d7400 xtensa: rework IRQ masking during IRQ entrance
Before cross stack call is setup correctly, we cannot allow
interrupts to be triggered or it may interfere with register
window spilling since we are clobbering registers needed for
that to work. However, there was a brief period where higher
level interrupts could fire due to code writing to PS with
lowered interrupt mask before raising it again. So rework
that part to avoid writing PS with intermediate value, and
now we mask interrupt until everything is setup correctly
before interrupt is enabled again.

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2025-04-17 00:57:19 +02:00
Daniel Leung
dcf75319e2 xtensa: set pointer to privileged stack only if user mode
When initializing the stack at thread creation, we should not
set the pointer to privileged stack pointer yet as the thread
can be a kernel thread. Only when a thread is transitioning to
user mode, then we need to set the pointer to point to
the privileged stack. This is a purely semantic change and
should not affect any functionality.

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2025-04-17 00:57:19 +02:00
Daniel Leung
d725f37d5e xtensa: userspace: calculate PC earlier at syscall entry
This moves the calculation of the return PC earlier in syscall
entry. There is no need to stash it into BSA, load it, do
the calculation and save it back. We can do the calculation
first and save it in BSA at the same time.

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2025-04-17 00:57:19 +02:00
Daniel Leung
1203ed05d9 xtensa: syscall: fix setting up PS for window spilling
We should not perform a straight OR operation on INTLEVEL as
we have no idea what existing PS.INTLEVEL is. Also, to avoid
any interferences, we disable interrupts very early during
syscall entrance. So we can remove the OR operation as
PS.INTLEVEL will still have all interrupts masked. Note that
we do not really need to OR PS_WOE into PS as we currently
only support windowed ABI which must have PS_WOE set in PS
anyway.

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2025-04-17 00:57:19 +02:00
Daniel Leung
7f693679b8 xtensa: move FPU_REG_SAVE out of ODD_REG_SAVE
Syscall entrance makes use of ODD_REG_SAVE but it does not
really need to save FPU registers as it is technically
the same thread and same context. So extract call to
FPU_REG_SAVE to interrupt handling code.

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2025-04-17 00:57:19 +02:00
Daniel Leung
c13c499557 xtensa: add ODD_REG_RESTORE
This adds ODD_REG_RESTORE as a counterpart to ODD_REG_SAVE.
Both the code in interrupt handling and syscall exit have
been refactored to use this new macro.

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2025-04-17 00:57:19 +02:00
Daniel Leung
fc85aface1 xtensa: parameterized ODD_REG_SAVE
This adds two parameters for ODD_REG_SAVE for scratch register
and BSA pointer, thus allowing a bit more flexibility on how
it can be called.

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2025-04-17 00:57:19 +02:00
Daniel Leung
10f8882eec xtensa: userspace: remove saving HiFi registers for syscalls
This removes the call to _xtensa_hifi_save() to save the HiFi
registers during syscalls. During syscall, we are not doing
context switching, and technically it is still the same thread.
There is no need to save HiFi registers.

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2025-04-17 00:57:19 +02:00
Daniel Leung
d9f6882071 xtensa: rsync before reading ZSR_FLUSH
The Xtensa ISA reference manual says to do rsync after wsr to
make sure register is updated before rsr. So do that.

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2025-04-17 00:57:19 +02:00
Daniel Leung
a4367eb514 xtensa: remove CONFIG_XTENSA_INVALIDATE_MEM_DOMAIN_TLB_ON_SWAP
Remove CONFIG_XTENSA_INVALIDATE_MEM_DOMAIN_TLB_ON_SWAP as it is
remnant from early MMU enabling work which is not needed as
the page table code is different from early version where
the PTEVADDR would be the same for all memory domains.

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2025-04-17 00:57:19 +02:00
Daniel Leung
ee9ddb0eeb xtensa: remove CALC_PTEVADDR_BASE and PRELOAD_PTEVADDR macros
These assembly macros are not being used at all. So remove
them.

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2025-04-17 00:57:19 +02:00
The Nguyen
949fc5b5f0 soc: renesas: add linker define for CMake Linker Generator on RA4E2
Initial support for CMake Linker Generator on Renesas RA4E2

Signed-off-by: The Nguyen <the.nguyen.yf@renesas.com>
2025-04-17 00:57:08 +02:00
Mika Braunschweig
d19c499037 drivers: interrupt-controller: vim: Compare interrupt numbers
To avoid misconfigurations a comparision has been added which compares the
amount of reported interrupts from the VIM interrupt controller with the
configured number of interrupts via Kconfig.

Signed-off-by: Mika Braunschweig <mika.braunschweig@siemens.com>
2025-04-17 00:56:59 +02:00
Mika Braunschweig
2b7db7f395 drivers: interrupt-controller: vim: Fix wrong address
On startup the VIM interrupt controller driver had a sys_read32 call with a
bitmask instead of an address. This has been fixed.

Signed-off-by: Mika Braunschweig <mika.braunschweig@siemens.com>
2025-04-17 00:56:59 +02:00
Eve Redero
cb8b1cdc74 dts: atmel: add adc node to due
Add ADC0 node and associated pincontrols
in sam3x and Arduino Due device trees.

Signed-off-by: Eve Redero <eve.redero@gmail.com>
2025-04-17 00:56:30 +02:00