In some cases the 'reschedule' code path is executed when the current
thread is the same as the next thread in the ready Q. If this happens,
the swap_return_value of the thread is ifalsely being reset to -EAGAIN.
This commit prevents the rescheduling code to run if the current thread
is the same as the thread in the ready Q.
Signed-off-by: Wolfgang Reißnegger <gnagflow@fb.com>
According to the rule MISRAC-2012 21.4.a the standard header
file <setjmp.h> shall not be used. Suppress it, because it raises
violation in a testcode, not in a runtime code.
Tag suppresses reporting of violation for the current file,
starting from the line where the suppression is located.
It is a deliberate deviation.
Found as a coding guideline violation (MISRA R21.4.a) by static
coding scanning tool.
Signed-off-by: Maksim Masalski <maksim.masalski@intel.com>
The driver code for the Maxim DS3231 has repeated code for bit
manipulation to transform time data between binary and binary coded
decimal. Use the new BCD header functions instead.
Signed-off-by: Jake Swensen <jake@swensen.io>
Some devices (such as RTCs) have data formats that expect BCD values
instead of binary. These routines allow for converting between binary
and BCD formats.
Signed-off-by: Jake Swensen <jake@swensen.io>
Low power modes entry on stm32wb depends on requests coming from both
cores, with no consideration of the fact that C2 is booted or not.
By default, set C2 power mode to shutdown at C1 start up.
If required, it will be updated by C2.
In case C2 is not started, this will allow C1 to enter any power mode
with no dependency on C2.
Fixes#38173
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
This adds arch_float_enable() and arch_float_disable() to x86-64.
As x86-64 always has FP/SSE enabled, these operations are basically
no-ops. These are added just for the completeness of arch interface.
Fixes#38022
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Some architectures already returns -ENOTSUP when these functions
are called. So add this return value to the API doc.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
This adds public API documentation for the thread bit
K_SSE_REGS. It was previously a single line comment.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Setting this bit will wake up CPU if it is in low power mode
and an interrupt is pending.
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
This adds shell support for FPGA drivers.
Signed-off-by: Mateusz Sierszulski <msierszulski@internships.antmicro.com>
Signed-off-by: Tomasz Gorochowik <tgorochowik@antmicro.com>
This adds driver for EOS_S3 SoC FPGA.
Signed-off-by: Mateusz Sierszulski <msierszulski@internships.antmicro.com>
Signed-off-by: Tomasz Gorochowik <tgorochowik@antmicro.com>
This adds new FPGA controller which allow to control FPGA chips.
FPGA controller has been created to enable bitstream loading
into the reprogrammable logic. It adds completely new API,
which enables to check status of the FPGA chip, power it on
or off and reset it.
Signed-off-by: Mateusz Sierszulski <msierszulski@internships.antmicro.com>
Signed-off-by: Tomasz Gorochowik <tgorochowik@antmicro.com>
The HiFive Unleashed and HiFive Unmatched boards do not enable the
SPI0 controller that the flash is connected to. This test will not
build on these platforms because SPI0 bus controller is missing.
Signed-off-by: Katsuhiro Suzuki <katsuhiro@katsuster.net>
This patch adds new support for SiFive HiFive Unmatched which has
SiFive FU740 SoC, DDR and some peripherals.
This is first version so not support all features on the board.
Signed-off-by: Katsuhiro Suzuki <katsuhiro@katsuster.net>
This patch adds support for SiFive Freedom U740 SoC.
First version is minimum only using UART, SPI and L2-LIM area.
Signed-off-by: Katsuhiro Suzuki <katsuhiro@katsuster.net>
This patch adds new support for SiFive HiFive Unleashed which has
SiFive FU540 SoC, DDR and some peripherals.
This is first version so not support all features of the board.
Signed-off-by: Katsuhiro Suzuki <katsuhiro@katsuster.net>
This patch adds support for SiFive Freedom U540 SoC.
First version is minimum only using UART, SPI and DDR memory area.
Signed-off-by: Katsuhiro Suzuki <katsuhiro@katsuster.net>
This patch changes condition of 'depends on' of sifive UART driver
to support other SoCs of SiFive Freedom series.
Signed-off-by: Katsuhiro Suzuki <katsuhiro@katsuster.net>
This patch fixes printf format specifier "%u" -> "%zu" for printing
an argument of size_t on 64bit environment.
Signed-off-by: Katsuhiro Suzuki <katsuhiro@katsuster.net>
add board support for Dragino NBSN95 NB-IoT sensor
node. Initial support only includes UART (with followup
patches on BC95 and other peripherals)
Signed-off-by: Parthiban Nallathambi <parthiban@linumiz.com>
Trivial change for C++, reorder Z_MEM_SLAB_INITIALIZER members
initialization in the same order they are defined in k_mem_slab
structure.
Fixes#38219
Signed-off-by: Lucas Dietrich <ld.adecy@gmail.com>
Add a very simple application intended to show how to use the Audio
DMIC API and also to be an aid in developing drivers to implement
this API.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Add a shim that allows using the nrfx PDM driver via the Zephyr API.
Add also missing devicetree nodes representing the PDM peripherals
in the nRF52 Series SoCs.
Extend the "nordic,nrf-pdm" binding with a new property that allows
specifying the clock source to be used by the PDM peripheral (so that
it is possible to use HFXO for better accuracy of the peripheral clock
or, in the nRF53 Series SoCs, to use the dedicated audio oscillator).
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
The name pinmux is misleading, since no actual pinmuxing is done (just
pull-up setup).
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
The internal pinmux API was being used to setup GPIO pull-ups, however,
this can be done using the standard GPIO API.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
After the Technical Steering Committee decided to approve the transition
from Slack to Discord, it is necessary to update all the documentation
to reflect this change.
Signed-off-by: Carles Cufi <carles.cufi@nordicsemi.no>
The free run timer will be used to count before entering hibernate
mode. Move the related registers to the head file for accessing.
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
Zephyr now requires CMake 3.20 or newer.
Let's remove comment regarding ADDITIONAL_CLEAN_FILES only supported
with CMake 3.15 or newer.
Also remove the ADDITIONAL_MAKE_CLEAN_FILES which provided the same
functionality, but only for Makefiles when using CMake <3.15.
Signed-off-by: Torsten Rasmussen <Torsten.Rasmussen@nordicsemi.no>
The `set_conf_file()` was deprecated in
6d4ba3490f
which is before Zephyr v1.14 LTS.
Let's remove the support now, before releasing a new LTS.
Signed-off-by: Torsten Rasmussen <Torsten.Rasmussen@nordicsemi.no>
This feature got written twice for two different purposes (to inform
the SOF app of which CPUs are running, and to predicate the delivery
of IPIs to the cores ready to receive the interrupt). Use only one.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
When working with the SOF kernel driver, it likes to shut down the DSP
on error. That means there is a very small window in which to catch
any log output, even with a whiteboxed kernel. So we should be
polling much faster (10 Hz) for changes when we detect a reset.
Also, don't repeatedly log the device reset detection, it spams the
console badly when we crank up the rate. Just log it once and then
stay silent until we see output.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
These are getting build failures due to some kind of devicetree
console definition missing. These devices don't do networking, and
strictly don't even have a proper console device (logging is done via
a host mechanism). Probably fixable. Not worth the trouble. Filter.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
On pre-2.5 cAVS, the initial IDC interrupt to start the other core is
handled by software in the firmware ROM. That means that it has to be
unmasked for the mechanism to work (with 2.5, the interrupt is handled
by hardware regardless of what the masking state in the interrupt
controller is).
Similarly, the Xtensa Region Protection Option entries have already
been set by ROM code when we arrive in enable_l1_cache(), so we can
skip that part on older machines. Also removed because trying to
rewrite those entries was causing inexplicable hangs on cAVS 1.5,
plausibly because the region had active cache lines.
(This patch is separate for easier review in a long evolving PR.
Technically it represents a bisection problem as the "New IDC Driver"
patch before this was a regression. Seems like a safe enough thing to
handle if you land on this.)
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
Fix various bugs with the new IDC layer that show up in edge cases
where code relies on correct timing of IPIs (unsurprisingly there is a
lot of code that recovers anyway even if the IPI doesn't arrive
promptly). Leaving this as a separate patch because the prior code in
the PR has already been reviewed and it "mostly" worked:
The unmasking of the L2 interrupt bit (remember there are three layers
of masking of the IDC interrupt) was always operating on CPU0 at CPU
startup because the code had been copied blindly. Unmask the CPU
we're actually launching. It turns out cAVS 2.x re-masks this on CPU
launch automatically.
The global init code to unmask all these interrupts at startup had the
same bug, even though it turned out to be needless (the initialization
state has it unmasked until it turns it back off). Do it right
anyway. Similarly add code to clear out existing interrupt latch
state by ACKing all IDC interrupts at startup. Seems needless, but
behavior isn't documented so let's be safe.
Flag CPU0 as always "active" for the purposes of IPIs. Forgot to do
this earlier, oops.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
The alignment on .bss was coming out wrong. The ". = ALIGN(4096);"
statement was being ignored, somewhat inexplicably. This resulted in
the bss symbols being assigned corret-seeming, non-overlapping
addresses. But it overlapped the page-sized padding at the end of
.data.
As it turns out, the rimage format (not the linker or Zephyr) requires
page-sized sections to copy, and the bootloader code does that copy by
writing to the CACHED mapping of the memory (.bss is, like .data,
uncached/coherent by default). So at runtime the CPU was running in a
context where the cache was populated with "booby trap" data at the
start of .bss. True .bss access would hit the memory uncached and see
the "correct" value, but at arbitrary times during execution lines
would be flushed out of L1 cache on top of it.
Oops. This was found by accident, actually, as routine changes to the
linker script to correctly support the case where KERNEL_COHERENCE=n
(i.e. put everything in the cached mapping and nothing in uncached)
suddenly hit rimage failures because of the overlap.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
New docs for cavs_v25 describe building a Linux kernel for a
Chromebook and need to talk about these kconfigs.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
