This adds a new qemu_x86_virt board where code and data are
mapped in virtual address space and is actually executing within
virtual address space.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Force the Arduino Due device to preform a reset after loading
the program using JLink, effectively allowing the program to
run after west flash.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
Commit 821c03a14a ("i2c: nordic: switch
to phandle arrays for pinmux") deprecated some Nordic devicetree
properties.
When boards get merged with stale CI results (i.e. if CI results are
from a mainline commit earlier than 821c03a1), we will get deprecation
warnings, which twister treats as errors.
Play whack-a-mole with the ones that are in tree.
Signed-off-by: Martí Bolívar <marti.bolivar@nordicsemi.no>
Enable the null-pointer dereferencing detection by default
throughout the test-suite. Explicitly disable this for the
gen_isr_table test which needs to perform vector table reads.
Disable null-pointer exception detection on qemu_cortex_m3
board, as DWT it is not emulated by QEMU on this platform.
Additionally, disable null-pointer exception detection on
mps2_an521 (QEMU target), as DWT is not present and the MPU
based solution won't work, since the target does not have
the area 0x0 - 0x400 mapped, but the QEMU still permits
read access.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
Convert driver and users of pinmux on mcux lpc platforms to getting
basic port info from devicetree (register address, label)
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Move the BOARD.dts files for Nordic-based boards to use the new I2C
devicetree properties for specifying the SDA and SCL pins.
This was done with a script.
Signed-off-by: Martí Bolívar <marti.bolivar@nordicsemi.no>
Convert ism330dhcx INT_PIN attribute from Kconfigs to Device
Tree binding properties. Here int-pin has been defined as
enum with two possible values: 1 and 2.
Signed-off-by: Armando Visconti <armando.visconti@st.com>
Add i2s as a supported feature on at least one board for each driver
that we have in tree to get CI coverage.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
If CONFIG_I2C=n is set we get a build warning:
pinmux.c:35:13: error: 'i2c_pinmux' defined but not used
Fix this by adding ifdef protection around i2c_pinmux.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
CONFIG_SPI_0 and CONFIG_SPI_0_OP_MODES aren't relevant for the
XEC QMSPI driver so remove setting them.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Add quadspi node in stm32f7.dtsi and quadspi support to boards
stm32f746g_disco and stm32f769i_disco.
Note! Does not support DMA.
Signed-off-by: Helge Juul <helge@fastmail.com>
Add pwm to board yaml as supported peripherals on the bbc_microbit.
This is needed as the servo_motor sample requires it.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
The board's main I2C bus controller doesn't have a compatible set, so
it's not detected as an I2C bus at all.
This breaks the build when trying to build the samples/sensor/lis2dh
application with the lis2dh sensor on that bus.
Fixes: #32420
Signed-off-by: Martí Bolívar <marti.bolivar@nordicsemi.no>
In NPCX7 series, it contains two tachometer (TACH) modules that contains
two Independent timers (counter 1 and 2). They are used to capture a
counter value when an event is detected via the external pads (TA or
TB).
The CL also includes:
— Add npcx tachometer device tree declarations.
— Zephyr sensor api implementation for tachometer.
— Enable "tach1" device in npcx7m6fb.dts for testing.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
This changes x86 to use CONFIG_SRAM_OFFSET instead of
arch-specific CONFIG_X86_KERNEL_OFFSET. This allows the common
MMU macro Z_BOOT_VIRT_TO_PHYS() and Z_BOOT_PHYS_TO_VIRT() to
function properly if we ever need to map the kernel into
virtual address space that does not have the same starting
physical address.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Place the new signing code in the TFM module CMakeLists.txt.
Make some small tweaks and add a sentence to the docs.
In the process, make a few changes to the signing code:
- Change some names of files created.
- Minimize the number of files created.
- Use hex files instead of bin files. This is so we don't need to know
the offset when creating hex files from bin files.
Also add signing for MCUBOOT_IMAGE_NUMBER=1 based on the code from the
v2m_musca_b1 board, though, this board does not build with =1 now
because of (I assume) some flash aliasing which places the S and NS
images 0x10000000 apart, where the manual algorithm places them next to
each other. It builds with =2, though.
Signed-off-by: Øyvind Rønningstad <oyvind.ronningstad@nordicsemi.no>
This CL introduces power management driver that improves the efficiency
of ec operation by adjusting the chip’s power consumption to the level
of activity required by the application in npcx series.
The following list summarizes the main properties of the various chip
power states. Please refer the power.c file for more detail.
Main power states in npcx series include:
- Active: Core, RAM and modules operate at the clocks generated by PLL.
- Idle: Enter this state when the Core executes WFI or WFE instruction.
- Sleep: clock is stopped for most of modules but PLL is enabled.
- Deep Sleep: As Sleep mode but PLL is disabled.
- Standby: All power rails are turned off besides standby and battery
power rails.
And this CL implements one power state, PM_STATE_SUSPEND_TO_IDLE, with
two sub-states for Zephyr power management system.
Sub-state 0 - "Deep Sleep" mode with “Instant” wake-up if residency
time is greater or equal to 1 ms
Sub-state 1 - "Deep Sleep" mode with "Standard" wake-up if residency
time is greater or equal to 201 ms
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
This CL introduces a kernel device driver implemented by the internal
64/32-bit timers in Nuvoton NPCX series. Via these two kinds of timer,
the driver provides an standard "system clock driver" interface.
It includes:
- A system timer based on an ITIM64 (Internal 64-bit timer) instance,
clocked by APB2 which freq is CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC.
- Its prescaler is set to 1 and provide the kernel cycles reading
without handling overflow mechanism.
- A event timer based on an ITIM32 (Internal 32-bit timer) instance,
clocked by LCLK which frequency is 32KHz and still activated when ec
entered "idle/deep idle" power state for better power consumption.
- Its prescaler is set to 1 and provide timeout event mechansim.
- Compensate system timer which clock is gating for better power
consumption after ec left"idle/deep idle" power state.
This CL passed starve, timer_api, and timer_monotonic test suites.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
When proper target device is specified, instead of generic
Cortex-M33, JLinkGDBServer is able to flash the device on "load"
command.
Signed-off-by: Seppo Takalo <seppo.takalo@nordicsemi.no>
Do not attempt to build/run all tests. Emulation platforms should
primarily build kernel and architecture related tests.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Quoting from the QEMU manual "MTTCG is not compatible with -icount and
enabling icount will force a single threaded run.". Given that for
Cortex-A53 we haven't seen any particular problem when disabling icount
try to disable it.
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
This driver emulates a EEPROM device in flash.
Reworked implementation with modified flash layout.
The emulation represents the EEPROM in flash as a region that is a
direct map of the eeprom data followed by a region where changes to
the eeprom data is stored. Changes are written as address-data
combinations. The size of such a combination is determined by the
flash write block size and the size of the eeprom (required address
space), with a minimum of 4 byte.
The eeprom page needs to be a multiple of the flash page. Multiple
eeprom pages is also so supported and increases the number of writes
that can be performed.
The eeprom size, pagesize and the flash partition used for the eeprom
are defined in the dts. The flash partition should allow at least two
eeprom pages. For fast read access a rambuffer can be enabled for the
eeprom (by setting the option rambuf in the dts).
Signed-off-by: Laczen JMS <laczenjms@gmail.com>
CLOCK_STM32_PLL_XTPRE Kconfig symbol default value is n.
Then there is no need to explicitly set it to 'n' in stm32f1 boards
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
The first uart instance was already devicetree based. To be consistent
convert the second instance to also be devicetree based.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
The choice allowed for using TFM's own default. We now need full
knowledge over whether BL2 is enabled or not (e.g. to do signing),
so remove this option and simplify to a bool.
Signed-off-by: Øyvind Rønningstad <oyvind.ronningstad@nordicsemi.no>
Add the missing pieces to enable XIP for AArch64. Try to simulate the
XIP using QEMU using the '-bios' parameter.
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
All x86 QEMU boards have a hard-coded memory size of 9MB which
does not corresponding with what is defined in device tree.
So make use of CONFIG_SRAM_SIZE to provide correct memory size.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
QEMU provides multiboot information by default so we can
use the provided memory map to mark reserved physical
memory. Note that 64-bit requires Multiboot2 which
currently both Zephyr and QEMU do not support, hence
it's not enabled for qemu_x86_64.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
