Commit graph

6 commits

Author SHA1 Message Date
Kumar Gala
fdd85d5ad7 dts: Rename DT_HAS_NODE macro to DT_HAS_NODE_STATUS_OKAY
Rename DT_HAS_NODE to DT_HAS_NODE_STATUS_OKAY so the semantics are
clear.  As going forward DT_HAS_NODE will report if a NODE exists
regardless of its status.

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2020-05-06 05:25:41 -05:00
Kumar Gala
5a31ee2175 soc: riscv: openisa_rv32m1: Convert to new dts macros
Convert from DT_OPENISA_RV32M1_INTMUX_INTMUX_LABEL to
DT_LABEL(DT_INST(0, openisa_rv32m1_intmux)).

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2020-04-29 08:03:24 -05:00
Kumar Gala
b263a3379c soc: riscv: openisa_rv32m1: Convert from Kconfig to DT_NODELABEL
As prep for drivers being converted to utilize DT_INST and removal of
per instance Kconfig symbols, move soc.c code to utilize DT_NODELABEL
instead.

Also rename various node labels to match the SoC docs.

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2020-04-10 14:38:04 -05:00
Henrik Brix Andersen
f3144644bd soc: riscv: rv32m1: enable peripheral clocks for Timer/PWM modules
Enable the peripheral clocks for the OpenISA RV32M1 Timer/PWM (TPM)
modules.

Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
2020-01-13 09:12:34 -06:00
Andrew Boie
4f77c2ad53 kernel: rename z_arch_ to arch_
Promote the private z_arch_* namespace, which specifies
the interface between the core kernel and the
architecture code, to a new top-level namespace named
arch_*.

This allows our documentation generation to create
online documentation for this set of interfaces,
and this set of interfaces is worth treating in a
more formal way anyway.

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2019-11-07 15:21:46 -08:00
Nicolas Pitre
1f4b5ddd0f riscv32: rename to riscv
With the upcoming riscv64 support, it is best to use "riscv" as the
subdirectory name and common symbols as riscv32 and riscv64 support
code is almost identical. Then later decide whether 32-bit or 64-bit
compilation is wanted.

Redirects for the web documentation are also included.

Then zephyrbot complained about this:

"
New files added that are not covered in CODEOWNERS:

dts/riscv/microsemi-miv.dtsi
dts/riscv/riscv32-fe310.dtsi

Please add one or more entries in the CODEOWNERS file to cover
those files
"

So I assigned them to those who created them. Feel free to readjust
as necessary.

Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
2019-08-02 13:54:48 -07:00
Renamed from soc/riscv32/openisa_rv32m1/soc.c (Browse further)