Replace all existing deprecated API with the recommended alternative.
Be aware that this does not address architectural errors in the use
of the work API.
Signed-off-by: Peter Bigot <peter.bigot@nordicsemi.no>
Replace all existing deprecated API with the recommended alternative.
Be aware that this does not address architectural errors in the use
of the work API.
Signed-off-by: Peter Bigot <peter.bigot@nordicsemi.no>
Replace all existing deprecated API with the recommended alternative.
Be aware that this does not address architectural errors in the use
of the work API.
Signed-off-by: Peter Bigot <peter.bigot@nordicsemi.no>
The parameter can be used to limit the ram and rom reports to a
certain depth. The resulting graphs with depths of e.g. 3 or 4 are
visually easier to grasp.
Signed-off-by: Detlev Zundel <dzu@member.fsf.org>
The script already accepts a depth parameter to configure the output,
but that parameter was not used at all. This commit adds the correct
handling by passing it to anytrees RenderTree iterator.
Signed-off-by: Detlev Zundel <dzu@member.fsf.org>
The TPM1/2 pin settings aren't used by any drivers or other devices and
only existed for testing purposes. Remove them since nothing in tree
is utilizing these settings.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
The nodelabel for the PWM controller on KW41Z is TPM[0..n], so we need
to change the logic in the ifdef to get the pins setup.
Additionally the setup of PORTA0/1 and PORTB16/17 pins for TPM only
exists on kPORT_MuxAlt5.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
There's no obvious reason that PTC11 should be as a GPIO pin when SPI0
is being utilized. As such remove this pin setting.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
The chipselect is wired to PTC4 and is SPI0_PCS0. Fix pinmux.c and
board docs to correctly reflect this.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Update eSPI buffer to values required per eSPI specification.
Allow applications to override as needed.
Guarantee buffers are not allocated at all if channels are
disabled.
Signed-off-by: Jose Alberto Meza <jose.a.meza.arellano@intel.com>
chan_send does restore buffer state in case of an error which is
different than how bt_l2cap_send_cb works as it does always unref in
case of an error.
Signed-off-by: Luiz Augusto von Dentz <luiz.von.dentz@intel.com>
This fixes a regression introduced by
10841b9a14 as it did remove a call to
net_buf_ref which was used not only to keep a reference for resending
but also to prevent bt_l2cap_send_cb to unref the buffer in case it
fails.
Signed-off-by: Luiz Augusto von Dentz <luiz.von.dentz@intel.com>
The log_core tests assume the logger is configured in
LOG_MODE_DEFERRED, so let's set it explicitly in the test
prj.conf instead of relaying on defaults.
+ fix a typo in test
Signed-off-by: Alberto Escolar Piedras <alpi@oticon.com>
Add parenthesis for the parameters to avoid the issues if
parameter is an expression but not an immediate value.
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Move the internal structs used by the generic, shared interrupt driver
from the public header file into the implementation file.
Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
In the time between a NODE_RX_TYPE_CONNECTION node is sent from LLL and
demuxed in ULL, an ADV role disable may be executed.
This makes the LLL data referenced in the node NULL/invald, and
ull_conn_setup would operate on invalid data.
This commit introduces a check in ADV disable to disallow the operation
(including conn invalidation), if a connection has been initiated.
To prevent pipeline-queued prepares from advertising after disable has
been initiated, set 'cancelled' flag for immediate signalling to LLL.
Signed-off-by: Morten Priess <mtpr@oticon.com>
Signed-off-by: Vinayak Kariappa Chettimada <vich@nordicsemi.no>
This commit is about the it8xxx2 analog to digital converter
driver. Support 8 channels ch0~ch7 and 10-bit resolution.
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
Add an entry in the release notes for 2.6, indicating
that TF-M is updated to v1.3.0 release.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
Zephyr socket subsystem has come a long way since initial experimental
alternative to internal Zephyr networking API. Its configuration also
mirrors the usual conservative approach, where a user needs to
explicitly enable options to get "more" features. And as an
experimental API, socket subsystem was initially developed as
namespaced API, where all functions/structures are prefixed with
"zsock_", and to get standard names, CONFIG_NET_SOCKETS_POSIX_NAMES
needs to be set (or alternatively, CONFIG_POSIX_API needs to be, which
enabled full POSIX subsys overall).
However, a few years later, sockets are the standard networking API,
and in majority of cases its used under the standard POSIX names.
Necessity to explicitly set an option to achieve this effects, and
confusion which results from it - are just unneeded chores for users.
So, switch CONFIG_NET_SOCKETS_POSIX_NAMES to be on by default (unless
CONFIG_POSIX_API is already defined). It still can be explicitly
disabled if needed (but usecases for that would be peculiar and rare).
Addresses #34165
Signed-off-by: Paul Sokolovsky <paul.sokolovsky@linaro.org>
Fixed the name of nodes in in espi-vw, miwu-wui, and miwu-int
device-tree node. This CL fixed missing nodes in CL d3a94fa8ab.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
The following is the interrupt priority plan for ec application.
The original IRQ priority map in Chromium EC is:
- IRQ priority 0:
|-ITIM IRQ for Warning watchdog.
-IRQ priority 1:
|-UART IRQ for signle byte FIFO in npcx5 series.
(Ignore it since UART has 16 bytes FIFO in npcx7 and later series.)
-IRQ priority 2:
|-SHI IRQ for FIFO FULL and Half FULL event.
|-MIWU IRQ for SHI CS. (Wake-Up ASAP for handling data from SPI bus.)
-IRQ priority 3:
|-All MIWU IRQs for GPIO, MTC and eSPI VW events.
|-ITIM IRQ for task scheduling.
|-ITIM IRQ for time-out.
(No need in Zephyr since 64-bit timer support.)
IRQ priority 4:
|-All UART FIFO IRQs
|-All I2C controller IRQs
|-ADC IRQ for conversion event.
|-ESPI IRQ for generic eSPI bus events.
|-Host KBC IBF/OBE IRQs
|-Host PM IBF/OBE IRQs
|-Host port80 IRQ
|-PECI IRQ
IRQ priority 5:
|-Keyboard RAW IRQ
|-PS2 IRQ
Then, this CL arranges the priority of npcx interrupts in Zephyr as:
IRQ priority 0:
|-Reserved it for further requirements.
IRQ priority 1:
|-SHI IRQ for FIFO FULL and Half FULL event.
| (Will modify it in ec repo.)
|-MIWU IRQ for SHI CS (Will modify it in ec repo.)
IRQ priority 2:
|-MIWU IRQ for GPIO, MTC, T0 timer and eSPI VW events.
|-ITIM IRQ for task scheduling.
IRQ priority 3:
|-All UART FIFO IRQs
|-All I2C controller IRQs
|-ADC IRQ for conversion event.
|-ESPI IRQ for generic eSPI bus events.
|-Host KBC IBF/OBE IRQs
|-Host PM IBF/OBE IRQs
|-Host port80 IRQ
IRQ priority 4:
|-Keyboard RAW IRQ. (Will modify it in ec repo.)
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
For i2c-devices, reg is the address. This took me way to long to
discover and I wanted to leave a breadcrumb for the next Zephyr newbie.
Signed-off-by: Jeremy Bettis <jbettis@chromium.org>
The functionality of the MPU depends on userspace, which has not
been implemented on AArch64. Therefore we skip that case for now.
Signed-off-by: Henry Wang <Henry.Wang@arm.com>
Add essential files to create a new board. Enable arch timer, uart,
multi-threading. Set memory map for flash and sram. The new board name
is fvp_baser_aemv8r with the fvp_aemv8r_aarch64 soc.
Signed-off-by: Jaxson Han <jaxson.han@arm.com>
This commit fixes the build error: "error implementation of
timestamp_serialize() not provided for your CPU target" for
fvp_baser_aemv8r tests.
Signed-off-by: Henry Wang <Henry.Wang@arm.com>
When ARM_MPU is defined, the MPU drivers will be built into the final
zephyr target.
Signed-off-by: Haibo Xu <haibo.xu@arm.com>
Signed-off-by: Jaxson Han <jaxson.han@arm.com>
Add several default mpu regions(flash/sram/sram_text/sram_ro) for
the Armv8-R aarch64 based Soc.
These regions will be initialized as static region during system boot.
Signed-off-by: Jaxson Han <jaxson.han@arm.com>
When MPU is enabled, the sections need to be 64 bytes aligned.
In the case of MMU, BSS section will be 4k aligned, because the first
variable in BSS section 'base_xlat_table' is explicitly aligned by
'__aligned(NUM_BASE_LEVEL_ENTRIES * sizeof(uint64_t))'.
However, with MPU, we do not have such a variable. So it's necessary
to fix the alignment of the BSS section in the linker.ld
Signed-off-by: Jaxson Han <jaxson.han@arm.com>
Armv8-R AArch64 MPU can support a maximum 16 memory regions, and the
actual region number can be retrieved from the system register(MPUIR)
during MPU initialization.
Current MPU driver only suppots EL1.
Signed-off-by: Haibo Xu <haibo.xu@arm.com>
Signed-off-by: Jaxson Han <jaxson.han@arm.com>
According to Armv8-R64 Spec, MPU related meta data(region base/limit)
is 64 bits. So we need to re-define MPU related data structure here.
Signed-off-by: Haibo Xu <haibo.xu@arm.com>
Signed-off-by: Jaxson Han <jaxson.han@arm.com>
Use -march=armv8.4-a to compile zephyr on cortex-R82.
Because Cortex-R82 has not been enabled in GCC 10.x currently.
Signed-off-by: Jaxson Han <jaxson.han@arm.com>
Add arm fvp emulator in order to use ninja run or west build -t run.
Add armfvp in order to run twister.
Set env ARMFVP_BIN_PATH before using it,
e.g. export ARMFVP_BIN_PATH=<path/to/fvp/dir>
NOTE: ARMFVP_BIN_PATH is the dir path.
Signed-off-by: Jaxson Han <jaxson.han@arm.com>
Add essential files to create a new soc.
Introduce a new type of soc series named fvp_aemv8r.
Add a new soc named fvp_aemv8r_aarch64.
Signed-off-by: Jaxson Han <jaxson.han@arm.com>
Add Cortex-R82 config to support the Cortex-R82 processor.
Introduce the new CPU_CORTEX_R_AARCH64 config for the Cortex-R 64-bit
processor.
Since the current CPU_CORTEX_R config has already been bound for
AArch32 in many test cases, we therefore add a new CPU_AARCH64_CORTEX_R
to distinguish from the Cortex-R 32-bit processor.
We do not use CPU_CORTEX_R64 because this name will lead to ambiguity
with processor name like Cortex-R82.
Signed-off-by: Jaxson Han <jaxson.han@arm.com>
If default config ARM_MMU is set to n, samples/tests will have
compilation error. This is because the arch/arm/aarch64/arm_mmu.h
is always included.
Signed-off-by: Henry Wang <Henry.Wang@arm.com>
When printing the unassigned values the 'sym' variable is
used as a dict from which we try to get the 'name' value.
However, 'symbols['unassigned']' gives a list of keys, so
we get an 'TypeError' when trying to access ['name'] of
a string (the key).
Fix this issue by iterating over the values from
the 'symbols['unassigned']' dict instead.
Signed-off-by: Håkon Øye Amundsen <haakon.amundsen@nordicsemi.no>
As of today we use second register bank only if fast interrupts are
enabled. So don't show the 'number of register bank' configuration
option if fast interrupts are disabled to avoid user confusion.
Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Signed-off-by: Evgeniy Paltsev <PaltsevEvgeniy@gmail.com>
