This patch will extend MMU mapping range for hwreg1 entry
because it is required to access lower register addresses
Signed-off-by: Adrian Bonislawski <adrian.bonislawski@intel.com>
This patch will set MMU permissions for .cold* sections
Fixes cold section execution if MMU is enabled
Signed-off-by: Adrian Bonislawski <adrian.bonislawski@intel.com>
This reverts commit 3d3ffa2c05.
The original commit aimed to prevent NULL pointer accesses by moving the
MMU mapping starting point one page later. However, this change has
caused a regression on PTL. Our DSP has registers with addresses lower
than 0x1000, and the firmware uses addresses starting from 0xC40. For
instance, the HDAMLDMICL register is located at 0xCC0, which is now
inaccessible due to the change.
Reverting this commit restores access to these critical registers and
resolves the regression issue.
Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
The MMU mapping in SoC covers 0x0 which prevents catching NULL
pointer accesses. Since there are no hardware registers at
the very first page of memory, we move the starting point one
page later.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
