Adds optional device tree properties to set delays between spi chip
select assert/deassert and clock edges in the mcux dspi and lpspi
drivers. If these properties are not set, then the minimum supported
delays are used.
Verified that tests/drivers/spi/spi_loopback/ still passes on
mimxrt1050_evk (lpspi driver) and frdm_k64f (dspi driver).
Measured with a scope that the pcs-sck-delay and sck-pcs-delay times on
the first spi transaction in the test are reduced from 7.82 us to 20 ns
on mimxrt1050_evk.
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
Select MPU_ALLOW_FLASH_WRITE when ARM_MPU is enabled, not CPU_HAS_MPU.
MPU_ALLOW_FLASH_WRITE is only defined as a symbol when ARM_MPU is
enabled. ARM_MPU is only defined when CPU_HAS_MPU is defined, so the
CPU_HAS_MPU dependency can be dropped.
This fixes a build error when MCUMGR_CMD_IMG_MGMT is enabled but
ARM_MPU is not.
Signed-off-by: Jordan Yates <jordan.yates@data61.csiro.au>
Add an additional option to the spi_cs_control struct that records how
the pin has been configured in devicetree. For drivers that are not
updated, the CS behaviour is the same as before (Push-Pull).
Use the devicetree knowledge with the GPIO subsystem so that the correct
physical pin levels for the CS pin are automatically selected.
Fixes#26267
Signed-off-by: Jordan Yates <jordan.yates@data61.csiro.au>
Add Nuvoton numicro series UART support, currently supports
only poll mode.
UART0 clock and pincontrol are directly configured, will be
replace when clock and gpio support is added.
Signed-off-by: Saravanan Sekar <saravanan@linumiz.com>
Add initial support for nuvoton numicro m48x SoC series, basic
init and uart functionality are covered with gpio and clock
directly relies on HAL.
Signed-off-by: Saravanan Sekar <saravanan@linumiz.com>
PCIe shell was enabled by default if shell is enabled in below commit:
commit ee985d81aa ("shell: enable modules by default if shell is
enabled").
However, this shell file has tests for PCIe RC, not applicable to EP.
So, should not be default enabled for PCIe EP.
If we add EP shell tests in future, they should be added under
drivers/pcie/endpoint/ directory.
Signed-off-by: Abhishek Shah <abhishek.shah@broadcom.com>
Add devicetree overlay for connecting an Mikroe ADC click shield to an
NXP LPCXpresso55S16 development board.
The LPCXpresso55S16 uses SSEL1 (CS1) for mikroBUS SPI, whereas the
generic Mikroe ADC click board definition assumes SPI CS0.
Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
Use the recently introduced mikrobus_spi devicetree node as parent node
instead of relying on mapping for arduino_spi.
Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
The Seeeduino XIAO is a tiny (20 mm x 17.5 mm) ARM development
board with onboard LEDs, USB port, and range of I/O broken out
onto 14 pins.
Signed-off-by: Michael Hope <mlhx@google.com>
Fixes whitespace in the frdm_kw41z shield document to allow continuation
in the numbered list of Bluetooth controller instructions and to format
the jumper configuration sublist correctly.
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
This enables PWM and connects it to the main LED. Tested by running
samples/basic/blinky_pwm and /fade_led.
Signed-off-by: Michael Hope <mlhx@google.com>
This runs the Timer/Counter for Control in 'normal' PWM mode. The
number of channels and counter width depends on the device and is
imported from DeviceTree.
Signed-off-by: Michael Hope <mlhx@google.com>
The SAMD21 series has three timer/counters with a mix of channels and
resolutions. Note that the SAMD20 only has TC peripherals and no TCC
peripherals which is why the changes are in samd21.dtsi.
Signed-off-by: Michael Hope <mlhx@google.com>
The SAM0 Timer/Counter for Control Applications can act as a counter
or generator. Add a binding for the TCC in PWM mode and helper to
check the compat mode.
Signed-off-by: Michael Hope <mlhx@google.com>
Fixes#26413.
The devicetree for disco_l475_iot1 declares the flash partitions
"storage" and "image-scratch" with overlapping address spaces.
As a result, when one of these partitions is used it can corrupt the
contents of the other one. This is the case when mcuboot performs an
image swap using the scratch partition.
To fix the bug, the size of the scratch partition is reduced.
Signed-off-by: Hans Wilmers <hans@wilmers.no>
In this board DT the "storage" and "image-scratch" are declared
with overlapping address spaces.
As a result, when one of these partitions is used it can corrupt the
contents of the other one. This is the case when mcuboot performs an
image swap using the scratch partition.
To fix the bug, the size of the scratch partition is reduced.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Use '0xa0' as default priority to be consistent with the V1/V2 and
V3 drivers default priority init.
Signed-off-by: Sandeep Tripathy <sandeep.tripathy@broadcom.com>
GICC_BPR has minimum legal values in secure and non-secure states.
'3' is the minimum BPR value leading to group and sub-group priority
as 'gggg.ssss'. In order to make an IRQ preemptible they need to
be in different priority group.
Hence to be generic priority values should be above '0x0f'.
IRQ0 - default priority (low prio)
IRQ1 - 0x0 (highest prio)
Signed-off-by: Sandeep Tripathy <sandeep.tripathy@broadcom.com>
