Commit graph

7 commits

Author SHA1 Message Date
Camille BAUD
72dadd3242 soc: wch: Introduce Qingke V4B
Introduces the Soc for ch32v203

Signed-off-by: Camille BAUD <mail@massdriver.space>
2025-05-14 11:02:52 +01:00
Camille BAUD
bab50a55de dts: wch: Enable using whole flash with CH32V208
Enables using the whole flash on CH32V208
This also involves limiting frequency of the CPU to 120Mhz
from 144Mhz to meet recommendations.

Signed-off-by: Camille BAUD <mail@massdriver.space>
2025-05-12 16:47:33 +02:00
64067e5d6a soc: wch: add the CH32V00x series
Compared to the CH32V003, the CH32V00x series is an evolution that
uses a different microarchitecture (V2C instead of V2A) and different
pinctrl mappings.

Fork the current qingke_v2a and use the new proposed naming convention.

Signed-off-by: Michael Hope <michaelh@juju.nz>
2025-05-09 01:40:22 +02:00
1d7a095779 soc: wch: move from qingke-v2 to the more specific qingke-v2a
The CH32V003 CPU is a QingKe V2A while others in the CH32V00x series
use the QingKe V2C. Prepare for adding support for the CH32V006 moving
to the more specifc qingke-v2a, moving some cases of SOC_CH32V003
actually meaning SOC_FAMILY_QINGKE_V2A.

Signed-off-by: Michael Hope <michaelh@juju.nz>
2025-04-26 10:55:45 +02:00
Camille BAUD
f67b321607 soc: Introduce Qingke V4C-based CH32V208 SoC
This introduces the only CH32 Serie Qingke V4C SoC, CH32V208

Signed-off-by: Camille BAUD <mail@massdriver.space>
2025-03-14 14:39:30 +01:00
Jianxiong Gu
74b502e914 soc: wch: add generic vector table support
Add `VECTOR_TABLE_SIZE` Kconfig option to define the number of interrupt
and exception vectors based on the actual hardware specification.

Signed-off-by: Jianxiong Gu <jianxiong.gu@outlook.com>
2025-01-15 11:58:58 +01:00
Jianxiong Gu
384144dc65 soc: wch: reorganize series directories by core
Place ch32v003 under the qingke_v2a series.
Place qingke series under the ch32v family.

Signed-off-by: Jianxiong Gu <jianxiong.gu@outlook.com>
2025-01-15 11:58:58 +01:00