Commit graph

11 commits

Author SHA1 Message Date
Jordan Yates
c3eeae80ec debug: thread_info: store arch mode_exc_return offset
Store the offset of mode_exc_return in the arch struct. This is required
to restore the link register to the original value, as `swap_helper.S`
saves the LSB to this field when `CONFIG_ARM_STORE_EXC_RETURN=y`.

Failing to account for this results in broken debugging when
`FPU_SHARING` or `ARM_NONSECURE_PREEMPTIBLE_SECURE_CALLS`.

Signed-off-by: Jordan Yates <jordan.yates@data61.csiro.au>
2022-10-28 11:51:15 +02:00
Kumar Gala
fc95ec98dd smp: Convert #if to use CONFIG_MP_MAX_NUM_CPUS
Convert CONFIG_MP_NUM_CPUS to CONFIG_MP_MAX_NUM_CPUS as we work on
phasing out CONFIG_MP_NUM_CPUS.

Signed-off-by: Kumar Gala <kumar.gala@intel.com>
2022-10-20 22:04:10 +09:00
Gerard Marull-Paretas
5113c1418d subsystems: migrate includes to <zephyr/...>
In order to bring consistency in-tree, migrate all subsystems code to
the new prefix <zephyr/...>. Note that the conversion has been scripted,
refer to zephyrproject-rtos#45388 for more details.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2022-05-09 12:07:35 +02:00
Julien Massot
f5f61ac605 debug: Add back openocd alias
OpenOCD is still using these alias, until we fix OpenOCD
upstream we should keep them.

This partially reverts commit
1a7bc06086.

Signed-off-by: Julien Massot <julien.massot@iot.bzh>
2022-02-02 14:34:41 -05:00
Maureen Helm
1a7bc06086 debug: Remove deprecated CONFIG_OPENOCD_SUPPORT
CONFIG_OPENOCD_SUPPORT was deprecated in favor of
CONFIG_DEBUG_THREAD_INFO in Zephyr v2.6.0 and can now be removed.

Signed-off-by: Maureen Helm <maureen.helm@intel.com>
2022-01-24 10:23:20 -05:00
Antony Pavlov
0369998e61 arch: add MIPS architecture support
MIPS (Microprocessor without Interlocked Pipelined Stages) is a
instruction set architecture (ISA) developed by MIPS Computer
Systems, now MIPS Technologies.

This commit provides MIPS architecture support to Zephyr. It is
compatible with the MIPS32 Release 1 specification.

Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
2022-01-19 13:48:21 -05:00
Daniel Leung
1672f6cea1 debug: thread_info: stack pointer is not supported for xtensa
Xtensa does not store the stack pointers in thread objects but
pushing the registers into the stack. There is no fixed location
to retrieve the stack pointer so mark it as unimplemented to
avoid the #warning.

Fixes #38405

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2021-09-09 19:06:38 -04:00
Gerson Fernando Budke
2797afb749 debug: thread_info: Add posix thread status
Add missing THREAD_INFO_OFFSET_T_STACK_PTR information for arch posix.

Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
2021-08-30 13:18:04 -04:00
Carlo Caione
256ca55476 arm64: Rework stack usage
The ARM64 port is currently using SP_EL0 for everything: kernel threads,
user threads and exceptions. In addition when taking an exception the
exception code is still using the thread SP without relying on any
interrupt stack.

If from one hand this makes the context switch really quick because the
thread context is already on the thread stack so we have only to save
one register (SP) for the whole context, on the other hand the major
limitation introduced by this choice is that if for some reason the
thread SP is corrupted or pointing to some unaccessible location (for
example in case of stack overflow), the exception code is unable to
recover or even deal with it.

The usual way of dealing with this kind of problems is to use a
dedicated interrupt stack on SP_EL1 when servicing the exceptions. The
real drawback of this is that, in case of context switch, all the
context must be copied from the shared interrupt stack into a
thread-specific stack or structure, so it is really slow.

We use here an hybrid approach, sacrificing a bit of stack space for a
quicker context switch. While nothing really changes for kernel threads,
for user threads we now use the privileged stack (already present to
service syscalls) as interrupt stack.

When an exception arrives the code now switches to use SP_EL1 that for
user threads is always pointing inside the privileged portion of the
stack of the current running thread. This achieves two things: (1)
isolate exceptions and syscall code to use a stack that is isolated,
privileged and not accessible to user threads and (2) the thread SP is
not touched at all during exceptions, so it can be invalid or corrupted
without any direct consequence.

Signed-off-by: Carlo Caione <ccaione@baylibre.com>
2021-04-23 06:32:20 -04:00
Carles Cufi
59a51f0e09 debug: Clean up thread awareness data sections
There's no need to duplicate the linker section for each architecture.
Instead, move the section declaration to common-rom.ld.

Signed-off-by: Carles Cufi <carles.cufi@nordicsemi.no>
2021-03-17 14:43:01 -05:00
Carles Cufi
d2465d6268 debug: Move away from openocd and make it generic
The exported structures that were originally introduced for OpenOCD have
since then been reused for other debugger plugins, including PyOCD and
Segger J-Link.

Rename the Kconfig option and the implementation from openocd to debug
thread info, so that it reflects the fact that this is no longer
specifically tied to OpenOCD.

Signed-off-by: Carles Cufi <carles.cufi@nordicsemi.no>
2021-03-17 14:43:01 -05:00