Commit graph

6 commits

Author SHA1 Message Date
Mazen NEIFER
0cfeb626c0 Xtensa port: Fixed scheduling bug caused to missing Endianess related macros.
XCC does neither define __BYTE_ORDER__ nor __ORDER_LITTLE/BIG_ENDIAN__ macros.
This resulted in field preempt of thread.base not correctly built from other
union fields prio and sched_locked, which caused wrong scheduling.

Change-Id: I8566ef4a5cf555906c012c4adc488f9afb26c053
Signed-off-by: Mazen NEIFER <mazen@nestwave.com>
2017-02-13 11:39:02 -08:00
Andrew Boie
9249f876a9 xtensa: cleanup fatal error handling
1) Fatal errors now all go through _SysFatalErrorHandler. When the
simulator is used, only the death of 'essential' threads will result
in the simulator exiting; some test cases that test exceptions may
actually expect a thread to terminate abnormally.

2) The human readability of the exception errors is improved.

Change-Id: I77f57ea0eae15b0c55237681b959cd21e3fe8c1c
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2017-02-13 11:39:02 -08:00
Mazen NEIFER
aacfd63331 Xtensa port: Removed duplicate file and renamed to sys_io.h as other platforms.
Change-Id: I293bfa9ff8c5e641c727612c56968cec901dbfec
Signed-off-by: Mazen NEIFER <mazen@nestwave.com>
2017-02-13 08:04:27 -08:00
Andrew Boie
73691609b9 xtensa: fix find_msb_set() and find_lsb_set()
find_msb_set logic was wrong. find_lsb_set() is now an inline function.

Change-Id: I2c19540907723589298b2f6af2ce1d68704bf1d7
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2017-02-13 08:04:27 -08:00
Andrew Boie
aa3ab35c88 xtensa: fixup license identifiers
Master branch changed requirements for license headers while this
branch has been in development.

Change-Id: I9bce16ff275057a4bb664019628fc9b6de7aef7c
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2017-02-13 08:04:27 -08:00
Mazen NEIFER
f7538f0005 Xtensa port: Added support in arch/cpu.h for Xtensa cores.
Change-Id: If4a053f6164fd2fa30f148e6e907f662cda50722
Signed-off-by: Mazen NEIFER <mazen@nestwave.com>
2017-02-13 08:04:27 -08:00