The LL_APBx_GRPn_ReleaseReset clears reset bit in RCC,
however this bit is reset by default. Code that set
this bit was removed in previous commit
0856e99155
Keepint the autonomous clocks for STM32U5 family.
Signed-off-by: Adam Berlinger <adam.berlinger@st.com>
Magic constants throughout the code made this difficult to reason about,
especially with two different units of measurement (bytes and words) at
play.
Signed-off-by: Armin Brauns <armin.brauns@embedded-solutions.at>
The RX FIFO size is in words, so needs to be subtracted from the total
memory size *after* it's divided by 4.
Fixes#70789.
Signed-off-by: Armin Brauns <armin.brauns@embedded-solutions.at>
Add driver for ST7796s display. This is a MIPI DBI display controller,
with a frame memory of 320x480x18 pixels. Support for 4 wire SPI mode is
implemented using the MIPI DBI API.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Warn about potential device tree errors for cases when driver's
client tries to configure a pin as GPIO but which is not
in GPIO mode.
Signed-off-by: Jose Alberto Meza <jose.a.meza.arellano@intel.com>
It is impossible to perform flash reads during a flash write. When the
data to write to flash lies in the flash itself, it is buffered in ram
before writing.
Signed-off-by: Lukas Gehreke <lk.gehreke@gmail.com>
Move providing of the first buffer in uart_rx_enable from that
function to the callback which is called from nrfx_uarte_rx_enable
context. By doing this nrfx_uarte_rx_buffer_set is called when
RX configuration flags are already known to the driver.
Signed-off-by: Krzysztof Chruściński <krzysztof.chruscinski@nordicsemi.no>
Provide support for reading events longer than 127 bytes in
ST SPI protocol v1 by splitting them into several SPI transactions.
Signed-off-by: Ali Hozhabri <ali.hozhabri@st.com>
Introduce NXP LCDIC driver using MIPI DBI class. This peripheral
supports 8080 and SPI 3/4 wire mode, although only SPI 4 wire support is
currently implemented. The driver supports DMA and interrupt driven
transfers.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
The soc_secure_* function are used by the non-secure application
to access hardware resources which are mapped as secure.
Using these functions for hardware resources mapped as non-secure
is missleading.
We have some soc_secure_* functions which read FICR values.
In nRF91 and nRF53 platforms this made sense since FICR
has hardware fixed mapping as secure.
For nRF54 though the FICR has hardware fixed mapping as non-secure.
This change refactors the soc_secure.h to exclude the functions
which read FICR values from being included when FICR is mapped as
non-secure.
Also updates the hwinfo and ieee802154 drivers to adjust to this change.
Signed-off-by: Georgios Vasilakis <georgios.vasilakis@nordicsemi.no>
Adds an option that allows for locking all interrupts when reading
the data from this sensor, this can be used alongside systems like
Bluetooth to vastly increase chances of getting a reading from the
sensor successfully, at the risk of losing Bluetooth packets.
Signed-off-by: Jamie McCrae <spam@helper3000.net>
User is able to enable packet capture for low level HDLC data
frames received from and sent to network. This data can sent to
remote system for analysis. The captured data is encapsulated
into Linux cooked mode SLL packets.
Signed-off-by: Jukka Rissanen <jukka.rissanen@nordicsemi.no>
Improve code consistency and fix CONFIG_POSIX_API=n compatibility with use
of ZSOCK_* and DNS_* macros.
Signed-off-by: Marcin Niestroj <m.niestroj@emb.dev>
The initial version of an input driver for Cirque Pinnacle ASIC supports:
* Setting sensitivity
* Choosing between relative and absolute modes
* Relative mode
* Primary tap
* Swapping X and Y
* Absolute mode
* Setting number of idle packets
* Clipping coordinates outside of active range
* Scaling coordinates
* Inverting X and Y coordinates
Signed-off-by: Ilia Kharin <akscram@gmail.com>
To prevent postponing data flush until filling fifo. Now the flush will
occur at the scheduled time, regardless of subsequent poll_out reqs.
Signed-off-by: Luis Ubieda <luisf@croxel.com>
A few lines above this change explicitly enable the UART FIFO. Then this
line, goes and disables it. This seems to be from a workaround where the
parity and stop bits are not coming in correctly in the config. Fixing
that will be another patch. But, the FIFO should always be enabled. This
is visible when trying to use bit rates that are reasonably fast. Even in
IRQ mode, with a sufficient bit rate, bytes are readily dropped.
Tested on a Sparkfun Promicro rp2040 board.
Signed-off-by: David Brown <david.brown@linaro.org>
