The compilation of the i2c_ll_stm32 fails when we
enable the interrupt mode. The struct i2c_stm32_data
is needed to initialize the semaphore. This patch adds
the missing struct for interrupt mode.
Signed-off-by: Yannis Damigos <giannis.damigos@gmail.com>
When transmitting to the UART interface using polled mode, the ESP32
driver would return 0 regardless of the success state. Return the
character that has been transmitted to comply with the API.
Jira: ZEP-2552
Signed-off-by: Leandro Pereira <leandro.pereira@intel.com>
Esp-idf defines the BIT macro that is also defined in Zephyr's
misc/util.h. Fix the issue by including the esp-idf headers first, so
that a check in util.h won't redefine the macro if it's already
defined.
Signed-off-by: Leandro Pereira <leandro.pereira@intel.com>
This exposes the CCM operations through generic Crypto API.
Change-Id: I09346e77bf8821c208305a7aa2805cf49cb42d71
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
'pad' parameter controls whether crc16() should add padding at the end
of input bytes or not. This allows to compute CRC16 for data stored in
non-contiguous buffers where CRC value is calculated using subsequent
calls to crc16() with padding added only for last chunk.
Signed-off-by: Andrzej Kaczmarek <andrzej.kaczmarek@codecoup.pl>
data_addr is not guaranteed to be word-aligned so we need to read it in
a safe way, otherwise this can trigger hardfault on nRF51.
Signed-off-by: Andrzej Kaczmarek <andrzej.kaczmarek@codecoup.pl>
Stop using CONFIG_I2C_x_DEFAULT_CFG to get the initial value. Since we
only support master mode we always default to it for initial config and
we get the bitrate from the device tree.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Stop using CONFIG_I2C_x_DEFAULT_CFG to get the initial value. Since we
only support master mode we always default to it for initial config and
we get the bitrate from the device tree.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Add _i2c_map_dt_bitrate() that maps from a bitrate to the I2C zephyr
cfg bit fields used in i2c_configure().
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Some targets (e.g. STM32-based boards) only have SPI drivers using the
new API. To support both these and existing, legacy SPI drivers in the
SPI HCI driver, abstract out the SPI API into shim routines.
There are no behavioral differences due to this patch. The next patch
will add support for the new API.
Signed-off-by: Marti Bolivar <marti.bolivar@linaro.org>
Per ZEP-1958, Phase 2 of adding CC3220sf LaunchXL support,
was to "deprecate the CC3200 launchxl support in Zephyr
(redundant to the CC3220)."
Effectively, the CC3220 SOC replaces the CC3200.
This patch removes the following:
* the imported CC3200 SDK
* CC3200 SOC, board, DTS files.
* adjusts other files where cc3200 was mentioned.
Also, it fixes explicit references to CC3200 in generic
CC32xx driver files.
Jira: ZEP-1958
Signed-off-by: Gil Pitney <gil.pitney@linaro.org>
ll_radio_state_is_idle() returns bool, not an error value - this means
it is non-zero on success.
Jira: ZEP-2445
Signed-off-by: Andrzej Kaczmarek <andrzej.kaczmarek@codecoup.pl>
Rename the BT_CONTROLLER prefix used in all of the Kconfig variables
related to the Bluetooth controller to BT_CTLR.
Signed-off-by: Carles Cufi <carles.cufi@nordicsemi.no>
Add support for TICKLESS KERNEL in nrf_rtc_timer for Nordic family of
processors. This patch includes :-
1. Programming RTC based on "next timer" value from timeout queue while
A. exiting idle_exit.
B. on RTC interrupt.
2. Impliments some of functions which will be required by sys_clock and
scheduler.
ZEP-1819
Signed-off-by: Youvedeep Singh <youvedeep.singh@intel.com>
This patch fixes the read operation of the I2C driver
for all the receptions (1-byte, 2-bytes, N-bytes when
N > 2)
Signed-off-by: Yannis Damigos <giannis.damigos@gmail.com>
Tested-by: Yannis Damigos <giannis.damigos@gmail.com>
Tested-by: Martin Iñaki Malerba <inakimmalerba@gmail.com>
In interrupt mode, the drivers entered a forever loop if the
I2C_MSG_RESTART flag was set. This patch fix this issue.
Signed-off-by: Yannis Damigos <giannis.damigos@gmail.com>
The EVENT interrupt is generated when:
– SB = 1
– ADDR = 1
– ADD10= 1
– BTF = 1 with no TxE or RxNE event
– TxE event to 1 if Buffer interrupt enabled
– RxNE event to 1 if Buffer interrupt enabled
We need to disable and enable the Buffer TxE and RxNE interrupt
inside the EVENT ISR. The LL_I2C_{Enable,Disable}IT_TX and
LL_I2C_{Enable,Disable}IT_RX functions, used now, enable and
disable both Buffer and Event interrupt. This patch uses the
LL_I2C_EnableIT_BUF and LL_I2C_DisableIT_BUF functions to
enable and disable the Buffer interrupt (TxE, RxNE).
Signed-off-by: Yannis Damigos <giannis.damigos@gmail.com>
* add nested interrupt support for interrupts
+ use a varibale exc_nest_count to trace nest interrupt and exception
+ regular interrupts can be nested by regular interrupts and fast
interrupts
+ fast interrupt's priority is the highest, cannot be nested
* remove the firq stack and exception stack
+ remove the coressponding kconfig option
+ all interrupts (normal and fast) and exceptions will be handled
in the same stack (_interrupt stack)
+ the pros are, smaller memory footprint (no firq stack), simpler
stack management, simpler codes, etc.. The cons are, possible
10-15 instructions overhead for the case where fast irq nests
regular irq
* add the case of ARC in test/kernel/gen_isr_table
Signed-off-by: Wayne Ren <wei.ren@synopsys.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Now that we have an mcux shim driver, remove the old k64-specific
driver. Also remove include/drivers/k20_sim.h, since the old
k64-specific driver was the only thing left using it.
Jira: ZEP-2025
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
Adds a shim layer around the mcux ftm driver to adapt it to the Zephyr
pwm interface.
Jira: ZEP-2025
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
The random number generator from ESP32 uses noise from Wi-Fi and
Bluetooth radios. If these are off, a pseudo-random number is
generated instead; this is currently the case, but even though it's a
black box, it's arguably better than returning a timestamp as a
pseudo-random number generator.
According to the ESP32 Technical Reference manual, the RNG passed the
Dieharder Random Number Test suite (version 3.31.1)[1], but nothing has
been said about the quality of the PRNG.
The RNG register is read directly; no effort is made to use its
contents to feed an entropy pool in a way that's similar to /dev/random
on POSIX systems, as no such subsystem exists on Zephyr at the moment.
[1] http://webhome.phy.duke.edu/~rgb/General/dieharder.php
Signed-off-by: Leandro Pereira <leandro.pereira@intel.com>
Zephyr's watchdog API is badly designed in the sense that it's a 1:1
abstraction on top of whatever Quark D2000 expects for its watchdog,
instead of expecting a generic timeout value.
This implementation tries as much as possible to calculate the watchdog
timeout in a way that's compatible with a Quark D2000 running at 32MHz;
a comment in adjust_timeout() explains this in more detail.
Jira: ZEP-2296
Signed-off-by: Leandro Pereira <leandro.pereira@intel.com>
This provides basic GPIO support, with interrupts, and the ability to
read and write to ports on a pin-by-pin basis.
Jira: ZEP-2286
Signed-off-by: Leandro Pereira <leandro.pereira@intel.com>
This implements a driver for the pin multiplexer as present in the ESP32
SoCs.
All APIs are supported.
Jira: ZEP-2297
Signed-off-by: Leandro Pereira <leandro.pereira@intel.com>
The alignment went off because of the move to use internal fixed-size
integer types (instead of standard int types).
Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
It used to be that there was a fairly empty "Bluetooth Drivers" menu
entry in the drivers menu. This entry was present even though there
was no drivers/bluetooth code being compiled in.
With this patch "Bluetooth Drivers" will no longer be present when
BT_CONTROLLER is enabled.
Signed-off-by: Sebastian Bøe <sebastian.boe@nordicsemi.no>
The CONFIG_BT_WAIT_NOP define is used only by
zephyr/subsys/bluetooth/host/hci_core.c.
It is also the only config in drivers/bluetooth that is in use when
BT_CONTROLLER is enabled. Moving it into the bluetooth subsystem
allows us to restructure the drivers/kconfig code such that the entire
Bluetooth driver menu option is omitted when the BT_CONTROLLER is
enabled.
Moving it will also mean that all configs in drivers/bluetooth will
now be related to configuring the source code in drivers/bluetooth.
Signed-off-by: Sebastian Bøe <sebastian.boe@nordicsemi.no>
Added function helps setting the longest possible rx and tx buffers for
single SPI transfer. Each of these buffers is a continuous memory
region. It is useful for example when peripheral supports easyDMA.
Signed-off-by: Michał Kruszewski <michal.kruszewski@nordicsemi.no>
The API name space for Bluetooth is bt_* and BT_* so it makes sense to
align the Kconfig name space with this. The additional benefit is that
this also makes the names shorter. It is also in line with what Linux
uses for Bluetooth Kconfig entries.
Some Bluetooth-related Networking Kconfig defines are renamed as well
in order to be consistent, such as NET_L2_BLUETOOTH.
Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
There are two kinds of HCI implementations. Bluetooth drivers in
drivers/bluetooth that implement HCI by using a wired serial
transport layer to talk to an external controller chip. And a
bluetooth controller in subsys/bluetooth/controller that directly
talks to an internal on-chip controller node.
Currently, when the the subsys/bluetooth/controller is used there
still exists exposed to the user a bluetooth driver configuration
menu, even though no external bluetooth driver is in use. This is due
to a dependency on certain configs in driver/bluetooth that are needed
even though no external controller is used.
This patch moves one of these configs, BLUETOOTH_HCI_RESERVE, from
drivers/bluetooth/hci/Kconfig to subsys/bluetooth/host/Kconfig such
that eventually we can omit the entire Bluetooth driver menu option.
This re-organization does not change when the config can be enabled.
Signed-off-by: Sebastian Bøe <sebastian.boe@nordicsemi.no>
The output state of the CS GPIO must be configured with a pull-up while
setting the GPIO as output. Otherwise the GPIO will be forced low,
before being set high by the call to spim_nrf52_csn(). This results in a
glitch of 1us on the CS line, which may confuse some ICs in the worst
case.
Signed-off-by: Florian Vaussard <florian.vaussard@gmail.com>
When setting the SPIM speed to 8 MHz, the driver will return an error
due to a missing "break" causing the execution flow to reach the default
case.
Signed-off-by: Florian Vaussard <florian.vaussard@gmail.com>
patch fix the dead code issue reported by coverity static scan
for gpio driver of cc2650 TI SOC. CC2650_IOC_NO_PULL macro
is defined Zero, bitwise and with any value would result to
zero,because of which only false condition of if is evaluated
but not the true condition.
Jira ZEP-2469.
Signed-off-by: Savinay Dharmappa <savinay.dharmappa@intel.com>
In Tickeless kernel Platform timekeeping is having error because
"_sys_clock_tick_count" is not getting updated correctly.
Currently "OVERFLOW" Flag (bit 16 in timer control register)
is reset before it is taken into account into _sys_clock_tick_count.
This patch sets a flag as soon as Timer Overflow occues and clears
it when time is accounted into _sys_clock_tick_count.
Jira : ZEP-2217
Signed-off-by: Youvedeep Singh <youvedeep.singh@intel.com>
The transmit and receive procedure used in the STM32 SPI driver is not
correct.
On STM32F4, this is causing OVR errors (per the logged error mask) and
transmission of undesired 0x00 bytes (verified with a logic analyzer).
The root cause is that the receive register is not read (via DR, when
RXNE is set) each time the transmit register is written (also via DR,
when TXE is set). This clearly causes OVR errors when there is no
FIFO, as the receive register needs to be read each time a frame is
transceived, or the IP block has no way of knowing that the
overwritten data were not important.
Adapt the I/O procedure so that every DR write is matched by a DR
read, blocking until the relevant flags are set if necessary.
This behavior is suboptimal for targets such as STM32L4, where there
is a SPI FIFO. However, SPI I/O is broken on those targets, and this
patch fixes them as well. Further optimizations for targets with FIFOs
is left to future work.
Signed-off-by: Marti Bolivar <marti.bolivar@linaro.org>
With some other issues in polled mode now resolved, add error handling
and report a valid error status when releasing the context.
Signed-off-by: Marti Bolivar <marti.bolivar@linaro.org>
Byte access is always naturally aligned; there's no need to use
UNALIGNED_GET or UNALIGNED_PUT. Those would only be needed when
supporting 16-bit data frames.
Signed-off-by: Marti Bolivar <marti.bolivar@linaro.org>
The current implementation unconditionally enables the SPI (sets
SPI_CR1_SPE) in transceive(), but disables it only in master mode.
The peripheral should only be enabled while the user has specifically
requested I/O. Fix this by always disabling the peripheral when I/O is
complete.
Signed-off-by: Marti Bolivar <marti.bolivar@linaro.org>
Polled and IRQ-driven SPI I/O share code for cleanup and completion,
which can now be factored into its own routine.
This keeps a single point of truth for common paths, which will allow
a subsequent bug fix to happen in one place, and help avoid future
regressions.
Signed-off-by: Marti Bolivar <marti.bolivar@linaro.org>
In polled mode, the STM32 SPI driver is signaling completion when
there are no waiters:
- the only spi_context_wait_for_completion() caller in this driver is
in the IRQ-driven portion of transceive() itself, which isn't
compiled in polled mode.
- the "asynchronous completion + polled I/O" combination is not
supported by the driver, so there are no other threads polling on
this I/O we need to signal completion to.
What should be happening instead of signaling completion is releasing
the chip select pin, which polled I/O currently doesn't do.
Fix these issues.
Signed-off-by: Marti Bolivar <marti.bolivar@linaro.org>
The LL_SPI_NSS_* macros used in spi_stm32_configure() when
hardware-based NSS management is requested are incorrect; fix them.
In master mode, this seems like a copy/paste error. The slave mode
case is likely due to following incorrect documentation in the ST LL
headers.
Note that in my testing on STM32F4, NSS appears to be open drain when
managed by hardware, making that configuration harder to test (and
probably less useful).
Details for the curious:
The ST LL headers (for example stm32f4xx_ll_spi.h) claim
LL_SPI_NSS_HARD_INPUT is to be used only in master mode, and
LL_SPI_NSS_HARD_OUTPUT is to be used in slave mode.
The opposite is true: when NSS is not handled by software, the SPI
peripheral is responsible for driving NSS as an output, and the
slave peripheral is responsible for reading it as an input.
This is an error in the LL header files; the reference manuals and
the other LL code make this clear.
- The ST reference manuals specify that LL_SPI_HARD_OUTPUT (which
corresponds to SSM unset, SSOE set) is a master-only
configuration. For example, STM32 RM0368 says:
"NSS output enabled (SSM = 0, SSOE = 1)
This configuration is used only when the device operates in
master mode."
- LL_SPI_HARD_INPUT (SSM unset, SSOE unset) is either a master or
a slave configuration; in the slave case (which is what we're
interested in here), it corresponds to the "usual" NSS
input. RM0368, again:
"NSS output disabled (SSM = 0, SSOE = 0)
This configuration allows multimaster capability for devices
operating in master mode. For devices set as slave, the NSS
pin acts as a classical NSS input: the slave is selected when
NSS is low and deselected when NSS high."
The LL_SPI_StructInit() implementations similarly combine
LL_SPI_MODE_SLAVE with LL_SPI_NSS_HARD_INPUT.
Signed-off-by: Marti Bolivar <marti.bolivar@linaro.org>
Now that struct spi_context supports passing errors from
interrupt-driven I/O handlers to waiting threads, we can enable error
interrupts and propagate errors to spi_transceive() callers.
To make it easier for users to debug SPI-related issues, log any error
bits set in SR when failures occur.
A subsequent patch will add error checking to polled mode as well, but
other cleanups and fixes will go in first to make this easier.
Note that this breaks the spi_loopback test on some targets, but it's
not a regression, as it wasn't working properly anyway. Subsequent
patches the bugs that this error checking has exposed.
Signed-off-by: Marti Bolivar <marti.bolivar@linaro.org>
The SPI API allows waiters to block until SPI I/O has completed. The
asynchronous subset of the API allows waiters to learn a status value
for the result of the I/O. However, the synchronous API does not allow
this.
Due to this limitation, synchronous API users cannot learn when
interrupt-driven I/O fails, which precludes proper error handling.
Resolve this limitation by adding a sync_status field to struct
spi_context, and using it to return operation results to the waiter.
Since there is only one status field, reduce the maximum number of
supported waiters from UINT_MAX to 1. This is not a problem for
current users, which all wait with the entire context locked.
Signed-off-by: Marti Bolivar <marti.bolivar@linaro.org>
Void pointer arithmetic is undefined behavior (UB).
It's OK for struct spi_buf to contain a void *, because those values
are only ever stored, read, and compared. However, pointer arithmetic
is done on the tx_buf and rx_buf fields in struct spi_context, so
those need to be u8_t * to avoid UB.
Signed-off-by: Marti Bolivar <marti.bolivar@linaro.org>
Add SPI pin mux tables for 96b_carbon. Note that SPI1 is for
internal use on the board connecting to the 96b_carbon_nrf51, while
SPI2 is broken out to an expansion header.
Signed-off-by: Marti Bolivar <marti.bolivar@linaro.org>
The ESP32 UART driver can only be used on the ESP32 SoC AFAICT. But it
did not have a depend clause so it was polluting the options of other
platforms.
With this patch the ESP32 driver will no longer be exposed to users of
non-ESP32 devices.
Signed-off-by: Sebastian Bøe <sebastian.boe@nordicsemi.no>
This patch implements following functionality in polling mode.
Ambient light
RGB light
proximity sensor
Following datasheet has been used to develop driver
https://docs.broadcom.com/docs/AV02-4191EN
Jira: ZEP-1552
Signed-off-by: Punit Vara <punit.vara@intel.com>
Fix clock polarity and phase configuration by using correct
bit shifted configuration values.
Also, fixed SPIM1 config struct initialization that referred
to wrong SPI0 value.
Signed-off-by: Nathan Loretan <nathan.loretan@nordicsemi.no>
As SLIP TAP is now the default after the commit ca0ad13a61
("net: enable SLIP only on QEMU targets"), clarify the comments
and settings in various Kconfig files that talk about slip.
Signed-off-by: Jukka Rissanen <jukka.rissanen@linux.intel.com>
Change the common "init with 0" + "give" idiom to "init with 1". This
won't change the behavior or performance, but should decrease the size
ever so slightly.
This change has been performed mechanically with the following
Coccinelle script:
@@
expression SEM;
expression LIMIT;
expression TIMEOUT;
@@
- k_sem_init(SEM, 0, LIMIT);
- k_sem_give(SEM);
+ k_sem_init(SEM, 1, LIMIT);
Signed-off-by: Leandro Pereira <leandro.pereira@intel.com>
Move to using the generated IRQ defines from the DTS instead of soc.h.
This change also fixes a minor bug in that the error irq priority wasn't
getting correctly picked up from device tree.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
This patch allows the use of the MCR20A driver with KW2xD devices.
The clock output of the transceiver can be used as an input clock
for the PLL of the SoC. The hardware reset and CLK_OUT setup of
the transceiver should then be performed during the initialization
of the SoC. The driver is not allowed to do it again.
Signed-off-by: Johann Fischer <j.fischer@phytec.de>
Some patches have been lost during rebase before the initial commit,
this path fixes it.
- correct copyright in registers definition header file
- fix undefined macro inside CLK_OUT configuration
- use the return value of k_sem_take if there is a timeout
Signed-off-by: Johann Fischer <j.fischer@phytec.de>
Following rework of pinmux driver for whole stm32 family,
remove call to stm32_get_pin_config which is no more
used.
Include dt-bindings stm32-pinctrl.h file to ensure coherency
between dts files and pinmux driver.
Due to change of "port" from enum to a series of define
(enum not accepted as dt binding), rework gpio_stm32_config
declaration.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
STM32F3 pinmux handler is reworked to support future pinmux dts
generation.
Preliminary change is done to move pin configuration
informations in a {pin, conf} structure closer to dts fields
"pins" array is removed as information is transfered to
"pinconf" array
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
STM32F4 pinmux handler is reworked to support future pinmux dts
generation.
Preliminary change is done to move pin configuration
informations in a {pin, conf} structure closer to dts fields
"pins" array is removed as information is transfered to
"pinconf" array
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Rework stm32f1 pinmux code for future dts based pinmux code
generation.
Pin configuration is now done directly thanks to gpio port
configuration. Reference to pseudo alternate functions are
now removed same as the use of pins[] array.
Pins function (uart tx for instance) is set implicitly by
defining gpio mode and configuration.
This behavior is specific to stm32f10x series.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
STM32L4 pinmux handler is reworked to support future pinmux dts
generation.
Preliminary change is done to move pin configuration
informations in a {pin, conf} structure closer to dts fields
"pins" array is removed and information is transferred to
"pinconf" array
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
The ethernet HAL has a different uint32_t typedef than Zephyr's u32_t:
uint32_t in the HAL is long unsigned int, while in Zephyr it's
unsigned int. This is causing a build warning on GCC ("warning:
passing argument 2 of ‘ENET_GetRxFrameSize’ from incompatible pointer
type") when passing a u32_t* where ENET_GetRxFrameSize expects a
uint32_t*.
Add a cast to silence the warning.
Signed-off-by: Marti Bolivar <marti.bolivar@linaro.org>
The net_stack_analyze function wants to look at the stack buffer,
but it is making assumptions on where this data is that are no
longer valid. Change to use the proper APIs for referencing this.
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
patch fix the dead code issue reported by coverity static scan
for gpio driver of cc2650 TI SOC. GPIO_DS_DFLT_LOW macro
is defined Zero, bitwise and with any value would result to
zero,because of which only false condition of if is evaluated
but not the true condition.This is a fix for jira ZEP-2355.
Signed-off-by: Savinay Dharmappa <savinay.dharmappa@intel.com>
Update the MCUX I2C driver and related platforms to get their I2C
information from the device tree. We also updated a few of the sensor
drivers found on the FRDM & Hexiwear boards to get their I2C bus name
from the device tree instead of directly from Kconfig.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Adds a shim layer around the mcux adc16 driver to adapt it to the Zephyr
adc interface.
Jira: ZEP-1396
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
Adds common and Kinetis-specific adc device tree properties, and updates
all Kinetis SoC and board dts files to include adc nodes.
Jira: ZEP-1396
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
The Kconfig assumed that there would only ever be one instance of an
adc, but some Kinetis devices have multiple adc instances.
Jira: ZEP-1396
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
As I2C_0 (port 0) isn't used on the STM32 platforms we didn't exclude
the related Kconfig options if DTS was enabled. However other SoCs
(like NXP) do use I2C_0 so we need to fixup the Kconfig dependencies
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
patch uses chosen property zephyr,bt-uart, zephyr,uart-pipe
and zephyr,bt-mon-uart to determine the uart instance to be
used for bluetooth,uart_pipe and bluetooth_monitor and generate
appropriate configs.
Signed-off-by: Savinay Dharmappa <savinay.dharmappa@intel.com>
It is incorrect to call spi_context_release() on a
spi_dw_data object's ctx field before data->ctx->config is first
set in spi_dw_configure(). This is because spi_context_release()
reads ctx->config->operation. In particular, during spi_dw_init(),
calling spi_context_release() reads the uninitialized memory in
spi->ctx->config->operation.
Call spi_context_unlock_unconditionally() instead to properly increase
the semaphore count.
Without this patch, the first call to spi_transceive() can block
forever depending on the value of the uninitialized memory holding
spi->ctx->config->operation.
Signed-off-by: Marti Bolivar <marti.bolivar@linaro.org>
It is incorrect to call spi_context_release() on an STM32
spi_stm32_data object's ctx field before data->ctx->config is first
set in spi_stm32_configure(). This is because spi_context_release()
reads ctx->config->operation. In particular, during spi_stm32_init(),
calling spi_context_release() reads the uninitialized memory in
data->ctx->config->operation.
Call spi_context_unlock_unconditionally() instead to properly increase
the semaphore count.
Without this patch, the first call to spi_transceive() can block
forever depending on the value of the uninitialized memory holding
data->ctx->config->operation.
Signed-off-by: Marti Bolivar <marti.bolivar@linaro.org>
Added BUILD_ASSERT check for Tx and Rx thread priorities.
The Tx thread priority shall be higher than Rx thread
priority in order to correctly detect transaction violations
in ATT and SMP protocols. The Number of Completed Packets
for a connection shall be processed before any new data is
received and processed for that connection.
The Controller's priority receive thread priority shall be
higher than the Host's Tx and the Controller's Rx thread
priority.
Signed-off-by: Vinayak Kariappa Chettimada <vich@nordicsemi.no>
Until Zephyr has infrastructure to enable/disable the
reception of multicast frames we disable the hardware
multicast frame filter completly and pass all multicast
frames to the upper layer and let that deal with them.
Signed-off-by: Erwin Rol <erwin@erwinrol.com>
We can use the chosen property "zephyr,console" to determine what uart
should be used as the console and find its name to generate a define for
CONFIG_UART_CONSOLE_ON_DEV_NAME.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Frequency tolerance for LFRC after calibration for nRF5x
Series ICs is between 251 and 500 ppm as per Product
Specification. For more details refer to:
http://infocenter.nordicsemi.com/
Signed-off-by: Vinayak Kariappa Chettimada <vich@nordicsemi.no>
By the time we get to POST_KERNEL, kernel services and kernel objects
should be available for use. This should include timers and the random
number generator, but we don't init the system clock until sometime
during the POST_KERNEL phase. Initialize it earlier.
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Upcoming memory protection features will be placing some additional
constraints on kernel objects:
- They need to reside in memory owned by the kernel and not the
application
- Certain kernel object validation schemes will require some run-time
initialization of all kernel objects before they can be used.
Per Ben these initializer macros were never intended to be public. It is
not forbidden to use them, but doing so requires care: the memory being
initialized must reside in kernel space, and extra runtime
initialization steps may need to be peformed before they are fully
usable as kernel objects. In particular, kernel subsystems or drivers
whose objects are already in kernel memory may still need to use these
macros if they define kernel objects as members of a larger data
structure.
It is intended that application developers instead use the
K_<object>_DEFINE macros, which will automatically put the object in the
right memory and add them to a section which can be iterated over at
boot to complete initiailization.
There was no K_WORK_DEFINE() macro for creating struct k_work objects,
this is now added.
k_poll_event and k_poll_signal are intended to be instatiated from
application memory and have not been changed.
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
The controller and host-side RX threads recently had their priorities
lowered to 8. Make the driver RX threads consistent with this.
Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
Configure I2C using DT for the following STM32 boards:
disco_l475_iot1
nucleo_f401re
96b_carbon
olimexino_stm32
Signed-off-by: Yannis Damigos <giannis.damigos@gmail.com>
The SAM4S, SAM3X, SAME70 all use the uart_sam.c serial
driver. This patch puts the configuration in DTS and
out of Kconfig. The SAME70 uses the USART as well.
USART DTS support for the SAME70 is also in this patch.
Signed-off-by: Justin Watson <jwatson5@gmail.com>
The I2C Slave Read support isn't well defined and not actually supported
by any i2c driver at this point. We can add this back when slave mode
is more thought out.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Add a STM32 LL based driver for the RNG processor. The RNG processor
is a random number generator, based on a continuous analog noise, that
provides a random 32-bit value to the host when read. The RNG passed
the FIPS PUB 140-2 (2001 October 10) tests with a success ratio of 99%.
Signed-off-by: Erwin Rol <erwin@erwinrol.com>
Add support for KW40Z in the KW41Z IEEE 802.15.4 driver as both chips
expose almost the same radio registers.
Signed-off-by: Bogdan Davidoaia <bogdan.davidoaia@linaro.org>
The chip seems to require a wait time before reading packet
data after the RX sequence done interrupt, as imidiate reading
of it will indicate a packet size of zero and cause the RX
sequence done to be continually retriggered.
In addition, the extra clearing of the interrupt flags can be
removed, as this is already done at the beginning of the isr.
Jira: ZEP-2278
Signed-off-by: Bogdan Davidoaia <bogdan.davidoaia@linaro.org>
When building tests/kernel/test_build/test_debug on disco_l475_iot1 we
get the following build error:
drivers/i2c/i2c_ll_stm32_v2.c: In function ‘stm32_i2c_configure_timing’:
ext/hal/st/stm32cube/stm32l4xx/soc/stm32l4xx.h:207:38: error: ‘timing’ may be used uninitialized in this function [-Werror=maybe-uninitialized]
#define WRITE_REG(REG, VAL) ((REG) = (VAL))
^
drivers/i2c/i2c_ll_stm32_v2.c:265:8: note: ‘timing’ was declared here
u32_t timing;
^~~~~~
Fix by initializing timing to 0.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Following implementation of LL based SPI driver,
add SPI support on nucleo_f334r8 board of STM32F3 series.
Change-Id: Ifbe39b1f2cecdd7db23be9c6943a914a155ebd77
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Add SPI pin for the nucleo_f401re pinmux.
Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Add a SPI master and slave driver for the L4, F4 and F3 STM32
SoCs families.
Change-Id: I1faf5c97f992c91eba852fd126e7d3b83158993d
Origin: Original
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Tested-by: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
Tested-by: Lee Jones <lee.jones@linaro.org>
As not all drivers support interrupts we don't have a means to know if
we can allow UART_INTERRUPT_DRIVEN to be enabled and thus various
Kconfig options that select UART_INTERRUPT_DRIVEN. Some drivers have a
interrupts, however not all do. So introduce a Kconfig option to let us
know what the driver actually supports.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
In added mode flash operation are performed in timeslice
(in radio idle time).
Kconfig for mode enabling CONFIG_SOC_FLASH_NRF5_RADIO_SYNC.
Erase and write API implementations were rewritten and preserved against
concurrent execution.
Signed-off-by: Andrzej Puzdrowski <andrzej.puzdrowski@nordicsemi.no>
Signed-off-by: Carles Cufi <carles.cufi@nordicsemi.no>
Add configuration, documentation, pinmux, fixup and dts support for
STM32F103x8 based Minimum System Development board.
Signed-off-by: Siddharth Chandrasekaran <siddharth@embedjournal.com>
as config SPI_CS_GPIO was selecting GPIO instead it
should just depend on it. This patch is a fix for
ZEP-2071 jira.
Signed-off-by: Savinay Dharmappa <savinay.dharmappa@intel.com>
patch enables qmsi serial driver to pick baudrate and name
from device tree instead of Kconfig for UART0 and UART1
instance
Signed-off-by: Savinay Dharmappa <savinay.dharmappa@intel.com>
The esp-idf package contains on the BSP a definition of the BIT macro
unconditionally #defined when rom/uart.h is #included. When Zephyr's
uart.h (which pulls in include/misc/util.h) that conditionally
This generates a compile warning on the re-definiton of BIT by the
esp-idf package.
Thus include uart.h after esp-idf's rom/uart.h to have BIT not
re-defined thanks to Zephyr's conditional definition.
Signed-off-by: Inaky Perez-Gonzalez <inaky.perez-gonzalez@intel.com>
This is a minimal driver enabling console output during the port
bringup. While the driver works, only one of the three UART devices
are supported, and there isn't any way to change any parameters or
use interrupts. This will most likely be superceded by a proper
driver after the port has matured.
Signed-off-by: Leandro Pereira <leandro.pereira@intel.com>
Update driver to use DTS-generated #defines for port names,
and not obsolete Kconfig variables.
Signed-off-by: Geoffrey Le Gourriérec <geoffrey.legourrierec@smile.fr>
L4 write access requires 64 bits alignment
while L4 read access does not require any alignment.
To support specific check according to read/write,erase
a parameter is added to stm32_valid_range.
Signed-off-by: Michel Jaouen <michel.jaouen@st.com>
L4 have 64 bits write access.
The cast to 64 bits data address in write_dword
requires 3 right shifts on i (byte index) else the
data taken are wrong for i different from 0
Signed-off-by: Michel Jaouen <michel.jaouen@st.com>
We always have UART_IRQ_FLAGS set to 0, so just call IRQ_CONNECT with a
0 argument for the flags, and remove the UART_IRQ_FLAGS. This is
towards support for using the driver on the TI CC2650. (we add a
comment about that as well).
Signed-off-by: Geoffrey Le Gourriérec <geoffrey.legourrierec@smile.fr>
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
This commit fixes the compilation error that occurs if both UART
ports on the FE310 SoC are enabled. The error occurs due to the
missing function definition of uart_fe310_irq_cfg_func_1 .
Signed-off-by: Jens Peter Schroer <jens@manetos.com>
Refactor internals of IPM driver removing bitfields and byte access of
32 bit registers.
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
The current method of accessing 32-bit data and control registers does
not work for all quark architectures. Sometimes writing to those
registers byte-by-byte results in last byte occupying whole 32 bit
register.
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Add necessary board files, pinmux and device tree in order to have a
usable debug console.
Origin: Original
Change-Id: I43a9d278c3f2c936a714263626722f630367b663
Signed-off-by: Florian Vaussard <florian.vaussard@heig-vd.ch>
Following migration of stm32f1xx series clock control driver to
STM32Cube LL API, cleanup stm32 code base in order to take into
account that this is the only clock driver available for stm32
family.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Following introduction of stm32cube LL based clock control driver,
remove references to former native driver.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Before introduction of LL based clock control for stm32f1xx series,
prepare gpio driver to provide useful definition for new API
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Align stm32f1xx series clock driver to other parts of stm32 family.
Driver support both Connectivity and Density lines of stm32f1 series,
that are based on different Reset and Clock Control architectures.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
The Nucleo STM32F413 board is missing the default pinmux for PWM2 on
PA0, as stated in the doc. The same pinmux is also done for other
similar Nucleo board. So add it!
Change-Id: I2086c0a4ce65d68455a0978570f118e965f4c6ca
Signed-off-by: Florian Vaussard <florian.vaussard@heig-vd.ch>
Atmel SAM3X series has been recently converted to use ASF
and should now use common SAM family drivers. The atmel_sam3
serial driver will be removed in the future.
Signed-off-by: Piotr Mienkowski <piotr.mienkowski@gmail.com>
Fix nRF RTC timer from returning more than actual cycles
in _timer_cycle_get_32, under race condition when ISR
announces to kernel.
Jira: ZEP-2229
Signed-off-by: Vinayak Kariappa Chettimada <vich@nordicsemi.no>
Instead of NULL terminated buffer arrays, let's add a parameter for each
that tells the number of spi_buf in it.
It adds a little bit more complexity in driver's side (spi_context.h)
but not on user side (bufer one has to take care of providing the NULL
pointer at the end of the array, now he requires to give the count).
This will saves a significant amount of bytes in more complex setup than
the current dumb spi driver sample.
Fix and Use size_t everywhere (spi_context.h was using u32_t).
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
The code was so far requesting 5 ms refresh timer, however with a
default TICKS_PER_SECOND=100 this was always rounded up to 10 ms,
causing some flickering. The closest TICKS_PER_SECOND that will give
flicker-less display but also give optimal ms-to-ticks calculations is
250, so change the timer to match that. After this change any code
using the display is recommended to set 250 as ticks per second.
Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
atmel_sam watchdog driver was temporarily limited to SAME70
series only. Now that all SAM series are using ASF the
change can be reverted.
Signed-off-by: Piotr Mienkowski <piotr.mienkowski@gmail.com>
Until we have better solution, we enable promiscuous mode as a
workaround to get IPv6 neighbour discovery going. Kconfig had
typos/thinkos preventing that to work however.
Signed-off-by: Paul Sokolovsky <paul.sokolovsky@linaro.org>
Source had CONFIG_ETH_MCUX_PHY_DETAILED_DEBUG, while Kconfig had
CONFIG_ETH_MCUX_PHY_EXTRA_DEBUG. Use the shorter name consistently.
Signed-off-by: Paul Sokolovsky <paul.sokolovsky@linaro.org>
Documentation doesn't specify if this function may return 0, so add an
inexpensive check to account for this.
Jira: ZEP-2135
CID: 160954
Signed-off-by: Leandro Pereira <leandro.pereira@intel.com>
If CS is controlled over GPIO, it will be possible to keep the slave up
and running (though no transaction will be going on) using this
configuration bit.
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
SPI_HOLD_ON_CS can be used to ask the SPI device to keep CS on, after
the transaction. And this undefinitely, until another config is used.
This will inhibate the gpio cs delay, if any. This might be useful when
doing consecutive calls on one slave without releasing the CS.
SPI_LOCK_ON is to be used with caution as it will keep the SPI device
locked for the current config being used after each transaction. This
can be necessary if one needs to do consecutive calls on a slave without
any olher caller to interfere.
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
All is done through the generic spi_context driver's API as it will be
generic to all SPI drivers.
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
Adding a struct k_poll_signal parameter to driver's API unique
exposed function.
If not NULL, the call will be handled as asynchronous and will
return right after the transaction has started, on the contrary
of current logic where is waits for the transaction to finish
(= synchronous).
In order to save stack, let's move the device pointer to struct
spi_config. So the call is still at a maximum of 4 parameters.
Adapting spi_dw.c and spi driver sample to the change so it still
builts.
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
All SPI drivers have this same way to handle synchronous call, thus
let's generalize it in struct spi_context, with a relevant API and apply
the change into SPI DW driver.
spi_context API will prove to be useful once asynchronous call will be
handled as well, through the same completion functions used now only for
synchronous call. It will be transparent for the driver.
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
Let's improve common SPI driver context by adding a lock and generic
function to get/release it.
It's statically initialized to save a bit of ROM.
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
Introducing as well a generic driver helper for CS gpio control and
buffer management.
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
Such API improves many aspects of the former API by reducing the number
of function, allowing more buffer flexibility etc... This leads in
better memory usag and performance as well.
However, as this will take sometime to get into use, the former API is
still present and is the one enabled by default.
Jira: ZEP-852
Jira: ZEP-287
Jira: ZEP-1725
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
One liners if/for/while statements still need {}
(and line break are cheap for clarity).
Aligning parameters properly.
Also, removing __func__ usage from SYS_LOG_* as these macros already put
it internally.
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
Removed the old PWM APIs usage and added support for the new PWM API.
JIRA: ZEP-2018
Signed-off-by: Adithya Baglody <adithya.nagaraj.baglody@intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
The data fragments were stored in reversed order when the RX
data was saved into network buffers. This was caused by net_pkt
changes in commit db11fcd "net/net_pkt: Fully separate struct
net_pkt from struct net_buf".
Signed-off-by: Piotr Mienkowski <piotr.mienkowski@gmail.com>
The STM32L4x SoCs embeds a slightly different embedded flash controller
from the STM32F4x SoCs.
This particular controller has the following properties :
- Up to 2 512KiB banks divided in 2KiB pages
- Flash can be accessed in any sizes
- Flash must be written in 64bit aligned 64bit double-words
The drivers/flash/flash_stm32f4x.c is refactored into a new common
drivers/flash/flash_stm32.c and drivers/flash/flash_stm32l4x.c is
created with the STM32L4x specific functions.
To ease the refactoring and keep common functions, the STM32L4x flash
headers are slightly modified to match the hardware reference naming
and solve compilation issues.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
A typo was present ion the erase and write function were bit were
uncorrectly unset but all other bit except the mask were unset.
The code still worked because the two typos fixed themselves.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Limit visibility of configurable TX pins to SAME70 series only.
Previously visibility of configurable SAME70 TX pins extended
to the full SAM family.
Signed-off-by: Piotr Mienkowski <piotr.mienkowski@gmail.com>
This patch converts Atmel sam3x MCU series to use register
header files from Atmel Software Framework (ASF) library.
By using ASF different Atmel SAM MCU series can use common
device drivers.
Signed-off-by: Piotr Mienkowski <piotr.mienkowski@gmail.com>
Now that we can utilize label in the device tree we can convert to
getting the device name for the Atmel SAM3 UART out of the device
tree instead of from Kconfig.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Now that we can utilize label in the device tree we can convert to
getting the device name for the TI Stellaris UART out of the device
tree instead of from Kconfig.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Now that we can utilize label in the device tree we can convert to
getting the device name for the TI CC32xx UART out of the device
tree instead of from Kconfig.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Now that we can utilize label in the device tree we can convert to
getting the device name for the ARM CMSDK APB UART out of the device
tree instead of from Kconfig.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Now that we can utilize label in the device tree we can convert to
getting the device name for the NXP Kinetis UART out of the device tree
instead of from Kconfig.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Now that we can utilize label in the device tree we can convert to
getting the device name for the NRF UART out of the device tree
instead of from Kconfig.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Now that we can utilize label in the device tree we can convert to
getting the device name for the STM32 UART out of the device tree
instead of from Kconfig.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Add configuration, pinmux, dts and documentation for the STM32L496G
Discovery board based on the STM32L496AG SoC.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
As we now only support DTS for ARM based SoCs we can remove any
associated !HAS_DTS bits in Kconfig. The Nordic NRF5 serial driver and
the ARM CMSDK APB serial drivers had Kconfig bits related to !HAS_DTS
builds.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Support for LSM6DSL accelerometer and gyroscpe sensor
with bare minimum features.
For more info on this sensor:
http://www.st.com/en/mems-and-sensors/lsm6dsl.html
Change-Id: I9b100a3e030faa8a70a5015a881025c876b81be4
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
i2c_burst_write API implementation in some driver
and generate a sequence of messages that does not allow to
communicate with LIS3MDL sensor. This commit replaces use
of i2c_burst_write with a call to i2c_write, which enables
sensor configuration.
Meanwhile, description of LIS3MDL is completed in sensor
header file.
Change-Id: Ib1b4643365f3c70b31fbfc4b0c30cff294b475a3
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Support for LPS22HB Pressure and temperature sensor provided
with bare minimum features.
For more info on this sensor:
http://www.st.com/en/mems-and-sensors/lps22hb.html
Change-Id: I14992b954053094beb054d0dba7581f6e29a3e68
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Add defines and pinmux arrays to support more UARTs on STM32F4.
Change-Id: Ib06c549bdb2b3d7065554a0a6d1a3d15441b29c9
Signed-off-by: Florian Vaussard <florian.vaussard@heig-vd.ch>
Add support for U(S)ART 4 to 10 that can be found at least on some
members of the STM32F4 family.
Change-Id: Ie870492511f885005cf023040e498bd4d800e807
Signed-off-by: Florian Vaussard <florian.vaussard@heig-vd.ch>
The registration of each serial port differs only by a few details.
These differences can be factorized in order to create a generic
registration macro.
This has several advantages:
- Less code
- Easier to add new ports
- Less work to add support for new STM32 families
Change-Id: I6e62a96ccbbf03c9d51bc2617db6a851ff0d83c7
Signed-off-by: Florian Vaussard <florian.vaussard@heig-vd.ch>
Add necessary board files, pinmux and device tree in order to have a
usable debug console.
Origin: Original
Change-Id: I280320700352fd36a544c03f4e57d2eeec2449e5
Signed-off-by: Florian Vaussard <florian.vaussard@heig-vd.ch>
The RX pin should be PA15 to use the Virtual COM port of the ST-LINK.
Also adds the missing entry in pinmux_stm32l4x.h.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
During introduction of LL clock_control driver on stm32f4 series,
AHB2 clock activation/deactivation case was let under stm32l4 condition
preventing activation of this clock with F4 series.
This patch fixes the issue.
Change-Id: I5e488e990d33252f491f8960fc7a798ca3416be2
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
uart_irq_tx_empty() function proved to be problematic: its semantics
was not documented properly, and many hardware uses terminology like
"TX register empty" to signify condition of TX register being ready
to accept another character (what in Zephyr is tested with
uart_irq_tx_ready()). To avoid confusion, uart_irq_tx_empty() was
renamed to uart_irq_tx_complete(), propagating to drivers/serial
device methods.
The semantics and usage model of all of uart_irq_rx_ready(),
uart_irq_tx_ready(), uart_irq_tx_complete() is now described in
detail.
Signed-off-by: Paul Sokolovsky <paul.sokolovsky@linaro.org>
Since more and more code is going to be reused by both the Host and the
Controller, this commit introduces a common/ folder that will contain
everything that is not tied to one of the two components but shared by
them.
Signed-off-by: Carles Cufi <carles.cufi@nordicsemi.no>
XT_* macros are defined in xtensa HAL headers as xcc intrinsics. gcc
does not have any of these intrinsics. Replace XT_* macros with inline
assembly or provide gcc-compatible definitions.
Change-Id: If823ea8a7898a11a3a8363b17efdba27dee4c6a4
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Commit 58c8d15 ("clock control:stm32: provide STM32Cube LL based
driver") added PLL initialization which disables the PLL before
configuring it.
This works if the system clock source is not the PLL (which is the
usual case for Zephyr booting out of chip reset). However, if the
SYSCLK source *is* the PLL, this halts execution.
To support this use case, switch the SYSCLK source to the
always-present HSI before disabling the PLL.
Signed-off-by: Marti Bolivar <marti.bolivar@linaro.org>
Factor out a subroutine used to switch SYSCLK to HSI. This code will
be used again in a subsequent patch.
Signed-off-by: Marti Bolivar <marti.bolivar@linaro.org>
Since the HCI driver debug option applies to both files in
drivers/bluetooth and subsys/bluetooth, the configuration option itself
now lives in the top-level Kconfig file for consistency.
Signed-off-by: Carles Cufi <carles.cufi@nordicsemi.no>
fix misspelling in Kconfig files that would show up in configuration
documentation and screens.
Signed-off-by: David B. Kinder <david.b.kinder@intel.com>
There is no need to unmask/mask the global transceiver interrupt
in kw41z_start/stop as the radio interrupt line is enabled/disabled
anyway with irq_enable/disable calls.
Signed-off-by: Bogdan Davidoaia <bogdan.davidoaia@linaro.org>
- set state to IDLE if TMR1 expires, but CCA reports channel as free
- no need to check for CCABFRTX, as the hardware isn't setup to do
CCA before TX
Signed-off-by: Bogdan Davidoaia <bogdan.davidoaia@linaro.org>
Sequence timeouts should be scaled to 16us, as TMR_PRESCALE was set
to 62.5kHz.
Also, radio warmup times and TX packet length need to be taken into
account.
Signed-off-by: Bogdan Davidoaia <bogdan.davidoaia@linaro.org>
The main difference to how the previous driver operates, is that this
version has zero-copy transmission. The transmit DMA descriptor is
updated for every fragment that is transmitted from the driver.
Another difference in the transmission path is that this version won't
spin indefinitely while waiting for the DMA transfer to complete; an
arbitrary number of busy checks (20) will be performed, and then
the transmission thread will yield for as long as necessary to finish
the transfer.
These two changes should fix ZEP-472; since that issue was opened for
an older version of Zephyr with uIP, I did not bother going all the way
back to test.
This has been only tested with a Galileo board, using Shared IRQ.
Jira: ZEP-1652
Jira: ZEP-472
Signed-off-by: Leandro Pereira <leandro.pereira@intel.com>
The purpose of irq_update() is to cache value of UART IRQ status
register for devices which needs such caching. No other driver
performs any other side effects in this call. For STM32, clearing
TC (tx complete) bit was introduced in 8c079e91c9
which is otherwise titled as a conversion to STM32Cube HAL. Thus,
there does not seem to be specific reasons why this code was added.
On the other hand, it leads to behaviorial artifacts when dealing
with interrup-driven UART code (specific issue seen was delaying
of transmitting every other character).
Change-Id: Id20bf214b36eeb6c09e29cc2e6bfca4f7221a1a4
Signed-off-by: Paul Sokolovsky <paul.sokolovsky@linaro.org>
* lis2dh 3 axis accelerometer support on SPI and I2C bus
* data ready and anymotion type of trigger support
Tested on Dynastream module D52QD2M4IA-A using SPI
Origin: based on Zephyr lis3dh driver
Change-Id: I2c4e9418b87f09c957bba8f73522bd78830bc809
Signed-off-by: Roger Lendenmann <roger.lendenmann@intel.com>
The files for the Arduino Due needed to be updated to use the new
configuration when the SoC moved from the atmel_sam3 directory to
the atmel_sam/sam3x directory.
Jira: ZEP-2067
Signed-off-by: Justin Watson <jwatson5@gmail.com>
SBCon is a simple device which allows directly setting and getting the
hardware state of two-bit serial interfaces like I2C. Therefore to be
useable we need to drive the lines with the appropriate protocol under
software control.
Change-Id: If9000bb75f7b0ad7bbb256b1cb38cc70fa6ca8ea
Signed-off-by: Jon Medhurst <tixy@linaro.org>
Several minor changes to clean up I2C Kconfig file
- align help text
- remove duplicate dependencies
- use unified naming for I2C port options
- replace outdated references to datasheet in help text
- add comments at the end of 'endif'
Change-Id: I452083feb29f40909e6e38324ff9d9961fc6bd07
Signed-off-by: Piotr Mienkowski <piotr.mienkowski@gmail.com>
The switch from C99 integer types to u16_t, etc. caused misalignment
in structs and function definitions with multi-line parameter lists.
Change-Id: Ic0e33dc199f834ad7772417bca4c0b2d2f779d15
Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
With recent changes we now have both SAME70 and SAM3X under
SOC_FAMILY_SAM so we need to limit the watchdog driver only to SAME70 as
it only builds there right now.
Change-Id: I4a7c90247ad22532b2384ca536cfb0cbd65186f9
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Converted Stellaris UART driver over to utilize device tree generated
defines. Added a yaml description for the uart, and converted over the
ti_lm3s6965 SoC & qemu_cortex_m3 board port over to utilize it.
Change-Id: Ie20844eb63d2c68eb59ad4160f7f5b5a35e2943b
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
There isn't any reason to export the uart_stellaris_isr function, so
lets make it static and remove the associated header file.
Change-Id: I3a131b584d9d6fb6279a1503512668a71510dd4d
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
This driver implements an I2C interface by driving two GPIO lines under
software control.
Change-Id: Ie49cc67aed6acb30086ee851041fe2470da241cf
Signed-off-by: Jon Medhurst <tixy@linaro.org>
This library implements the I2C single master protocol in software.
It supports the Standard-mode and Fast-mode speeds and doesn't support
optional protocol feature like 10-bit addresses or clock stretching.
Change-Id: I375d572a83714522421f2967dc414b3bec169e95
Signed-off-by: Jon Medhurst <tixy@linaro.org>
Clean-up the pinmux header as a preparatory work before adding more
pinmuxes.
This is achieved by the following two actions:
- Reorder the defines by increasing GPIO order to make it
easier to add more pinmux over time while avoiding a huge mess
- Use tabs to align
Change-Id: I07d9ae28f61287748d33dcf638dcbf2e6865517b
Signed-off-by: Florian Vaussard <florian.vaussard@heig-vd.ch>
This commit provides support for disco_l475_iot1 board
Pinmux driver is provided with initial support definitions
Change-Id: I17b637a8ba0b033014969eca8fffe76319c47c52
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Adds a shim layer around the mcux lpsci driver to adapt it to the Zephyr
serial interface.
Change-Id: I024f1605e3194f34bb57e8a121900e05b3085a82
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
This commits align CONFIG_ factor names between stm32f4 and stm32l4
series to enable code factorization such as use of Q_DIVISOR.
Though, it does not concatenate kconfig sections as we might use
a bit of time to see what is needed in this regard
Change-Id: Ia603406d53949abf5675b801a5448397d5ab8462
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Small code refactorisation in order to ease up coming
support of stm32f1 series by stm32 commom clock control
driver
Change-Id: I486cfba137cd048d65f0732e10aa29d877bb03e5
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Following activation of stm32 common clock driver for stm32f4 series
remove references to stm32f4 specific driver.
Change-Id: I372a0ea046007bcb34944d6b2b8880077583b1d3
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Following update of LL clock driver to suport F4 series,
update dma driver to support LL clock driver API.
Change-Id: Ic8ecfe4f33109204f3b5f8c22bcb9c41de81531d
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
This commit enables STM32Cube LL based driver for stm32f4 series.
This generic driver provides a unified API to clock driver for all
stm32 series.
LL API allows driver to be lightweight and to keep genericity across
stm32 family to ease further devlopment and maintenance.
Change-Id: Ie31ae8f433313787f9c9eda77de41925721d54dd
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Devicetree.org specifies that serial devices property used to set
baud rate is "current-speed", while zephyr uses "baud-rate".
Align property name in order to keep zephyr dts files compatible
with device tree specification and could be re-used from/to
Linux for instance. We also cleanup a few SoCs that set "baud-rate" in
the SoC dts and not the board.
Jira: ZEP-2048
Change-Id: I097e7439ee46fe77c628b56531772950382fafcc
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
The data fragments were stored in reversed order when the RX
data was saved into network buffers. This was caused by net_pkt
changes in commit "net/net_pkt: Fully separate struct net_pkt
from struct net_buf".
Change-Id: I8ad2cfc23b2cb90896b0548eab168895b0d7421d
Signed-off-by: Jukka Rissanen <jukka.rissanen@linux.intel.com>
For stream-based protocols (TCP), adding less data than requested
("short write") is generally not a problem - the rest of data can
be sent in the next packet. So, make net_pkt_append() return length
of written data instead of just bool flag, which makes it closer
to the behavior of POSIX send()/write() calls.
There're many users of older net_pkt_append() in the codebase
however, so net_pkt_append_all() convenience function is added which
keeps returning a boolean flag. All current users were converted to
this function, except for two:
samples/net/http_server/src/ssl_utils.c
samples/net/mbedtls_sslclient/src/tcp.c
Both are related to TLS and implement mbedTLS "tx callback", which
follows POSIX short-write semantics. Both cases also had a code to
workaround previous boolean-only behavior of net_pkt_append() - after
calling it, they measured length of the actual data added (but only
in case of successful return of net_pkt_append(), so that didn't
really help). So, these 2 cases are already improved.
Jira: ZEP-1984
Change-Id: Ibaf7c029b15e91b516d73dab3612eed190ee982b
Signed-off-by: Paul Sokolovsky <paul.sokolovsky@linaro.org>
This patch adds support for reading MAC address from I2C EEPROM.
Only chips with 7-bit I2C device address are supported.
Change-Id: Ibedc33e54e33bdb901840e104063e2f4752b9123
Signed-off-by: Piotr Mienkowski <piotr.mienkowski@gmail.com>
Otherwise they are send as is and stripped by tunslip6, resulting in
malformed packets.
Jira: ZEP-2037
Change-Id: I1267b9ac956f3cd7aa3456ce20447ef97281d7a8
Signed-off-by: Ruslan Mstoi <ruslan.mstoi@intel.com>
Don't busy-wait in uart_stm32_fifo_fill(), this routine is supposed
to be called on IRQ, and the waiting loop was shown to interfere
with interrupt-driven UART handling.
The original problem mentioned in the patch being reverted ("it is
possible to evaluate the TXE bit *before* H/W has had the
opportunity to detect that data is being processed") may still
exist and may require handling in a different way. The most obvious
way is to replace "while" loop with "if", because STM32 doesn't
have multi-level FIFO anyway. But I was dissuaded to include such a
change as part of this patch, so it's left for future analysis.
This reverts commit 49c2858d94.
Change-Id: Ib27b53ba3a29b84c1a2dccff6d33f4118680cc19
Signed-off-by: Paul Sokolovsky <paul.sokolovsky@linaro.org>
Add tickless kernel support. Sets timer always in one
shot mode to the time the kernel scheduler needs the
next timer event. Uses mili seconds as the scheduling
time unit.
Jira: ZEP-1817
Change-Id: Ia2e63711cdd9d7d9c241b9ff08a606aa79575012
Signed-off-by: Ramesh Thomas <ramesh.thomas@intel.com>
Add tickless kernel support. Sets timer always in one
shot mode to the time the kernel scheduler needs the
next timer event. Uses mili seconds as the scheduling
time unit.
Jira: ZEP-1818
Change-Id: I21ce037b571c4c6ff588033a15aa49624cba7a57
Signed-off-by: Ramesh Thomas <ramesh.thomas@intel.com>
Add tickless kernel support. Sets timer always in one
shot mode to the time the kerneel scheduler needs the
next timer event. Uses mili seconds as the scheduling
time unit.
Jira: ZEP-1816
Change-Id: I85232b572759b9653c6396edc057ff4409525c97
Signed-off-by: Ramesh Thomas <ramesh.thomas@intel.com>
Update the timer to use the tickless kernel interface
provided by kernel to operate in event based mode. In
this mode, the timer would not generate periodic ticks
and would only be programmed in one shot mode. It would
announce elapsed time in wall time units instead of
ticks. Timer can also be disabled enabling waiting
forever for a non-timer event.
Jira: ZEP-1812
Change-Id: I13110b9fb53b33a9244cc91a3d991f8452d330b1
Signed-off-by: Ramesh Thomas <ramesh.thomas@intel.com>
Adds event based scheduling logic to the kernel. Updates
management of timeouts, timers, idling etc. based on
time tracked at events rather than periodic ticks. Provides
interfaces for timers to announce and get next timer expiry
based on kernel scheduling decisions involving time slicing
of threads, timeouts and idling. Uses wall time units instead
of ticks in all scheduling activities.
The implementation involves changes in the following areas
1. Management of time in wall units like ms/us instead of ticks
The existing implementation already had an option to configure
number of ticks in a second. The new implementation builds on
top of that feature and provides option to set the size of the
scheduling granurality to mili seconds or micro seconds. This
allows most of the current implementation to be reused. Due to
this re-use and co-existence with tick based kernel, the names
of variables may contain the word "tick". However, in the
tickless kernel implementation, it represents the currently
configured time unit, which would be be mili seconds or
micro seconds. The APIs that take time as a parameter are not
impacted and they continue to pass time in mili seconds.
2. Timers would not be programmed in periodic mode
generating ticks. Instead they would be programmed in one
shot mode to generate events at the time the kernel scheduler
needs to gain control for its scheduling activities like
timers, timeouts, time slicing, idling etc.
3. The scheduler provides interfaces that the timer drivers
use to announce elapsed time and get the next time the scheduler
needs a timer event. It is possible that the scheduler may not
need another timer event, in which case the system would wait
for a non-timer event to wake it up if it is idling.
4. New APIs are defined to be implemented by timer drivers. Also
they need to handler timer events differently. These changes
have been done in the HPET timer driver. In future other timers
that support tickles kernel should implement these APIs as well.
These APIs are to re-program the timer, update and announce
elapsed time.
5. Philosopher and timer_api applications have been enabled to
test tickless kernel. Separate configuration files are created
which define the necessary CONFIG flags. Run these apps using
following command
make pristine && make BOARD=qemu_x86 CONF_FILE=prj_tickless.conf qemu
Jira: ZEP-339 ZEP-1946 ZEP-948
Change-Id: I7d950c31bf1ff929a9066fad42c2f0559a2e5983
Signed-off-by: Ramesh Thomas <ramesh.thomas@intel.com>
If setting up crypto context fails enough times, the sessions will all
end up "in use" though they will not. This will lock tc shim driver
altogether and no crypto context will be possible to run on it.
Change-Id: I72346854e52294f96afc32f30ac5bfd0c368812b
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
Thus it is possible to reduce or raise such amount relevantly if
required.
Change-Id: Ib53131e10e69fcbf1bcd9d844703d5b8832ee224
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
All existing log entries add a line break, so let's just use the sys_log
way.
Change-Id: Ia94efa593700e9590e16b51262f0b5a2fe10ffa2
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
As everywhere else in drivers, domain of driver should be used as name
prefix.
Change-Id: I1bb2284495c7a6b2648395b757a5f912e4410b15
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
As it is a crypto driver, let's prefix all options with CRYPTO_ as it is
done everywhere else.
Change-Id: I1eccbf655417664a1f031a221081b0b1db673394
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
- help message should have same intendation on a specific file
- No need of "depends on" if it's already in a relevant if/endif
- either prompt is used, or not, but let's not mix.
Change-Id: Ib75f25dcf2440fd0ba7bde5c95bc1fbece68be07
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
Fix misspellings in Kconfig help text and made spelling of
RX and TX consistent (from reviewer comments)
Change-Id: Ie9d4c3863cd210e7a17b50a85a7e64156b6bf3d7
Signed-off-by: David B. Kinder <david.b.kinder@intel.com>
Convert code to use u{8,16,32,64}_t and s{8,16,32,64}_t instead of C99
integer types. This handles the remaining includes and kernel, plus
touching up various points that we skipped because of include
dependancies. We also convert the PRI printf formatters in the arch
code over to normal formatters.
Jira: ZEP-2051
Change-Id: Iecbb12601a3ee4ea936fd7ddea37788a645b08b0
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Even one liner if () should have get { ... }
Change-Id: I7f9d8d74398286e97549bed050e29d4d175e1b02
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
Convert code to use u{8,16,32,64}_t and s{8,16,32,64}_t instead of C99
integer types.
Jira: ZEP-2051
Change-Id: I08f51e2bfd475f6245771c1bd2df7ffc744c48c4
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Convert code to use u{8,16,32,64}_t and s{8,16,32,64}_t instead of C99
integer types.
Jira: ZEP-2051
Change-Id: I4ec03eb2183d59ef86ea2c20d956e5d272656837
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
- net_pkt becomes a stand-alone structure with network packet meta
information.
- network packet data is still managed through net_buf, mostly named
'frag'.
- net_pkt memory management is done through k_mem_slab
- function got introduced or relevantly renamed to target eithe net_pkt
or net_buf fragments.
- net_buf's sent_list ends up in net_pkt now, and thus helps to save
memory when TCP is enabled.
Change-Id: Ibd5c17df4f75891dec79db723a4c9fc704eb843d
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
There have been long lasting confusion between net_buf and net_nbuf.
While the first is actually a buffer, the second one is not. It's a
network buffer descriptor. More precisely it provides meta data about a
network packet, and holds the chain of buffer fragments made of net_buf.
Thus renaming net_nbuf to net_pkt and all names around it as well
(function, Kconfig option, ..).
Though net_pkt if the new name, it still inherit its logic from net_buf.
'
This patch is the first of a serie that will separate completely net_pkt
from net_buf.
Change-Id: Iecb32d2a0d8f4647692e5328e54b5c35454194cd
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
Convert code to use u{8,16,32,64}_t and s{8,16,32,64}_t instead of C99
integer types.
Jira: ZEP-2051
Change-Id: I8f57a17f78e674aca5400f005db8975c9f9e150e
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
This is a start to move away from the C99 {u}int{8,16,32,64}_t types to
Zephyr defined u{8,16,32,64}_t and s{8,16,32,64}_t. This allows Zephyr
to define the sized types in a consistent manor across all the
architectures we support and not conflict with what various compilers
and libc might do with regards to the C99 types.
We introduce <zephyr/types.h> as part of this and have it include
<stdint.h> for now until we transition all the code away from the C99
types.
We go with u{8,16,32,64}_t and s{8,16,32,64}_t as there are some
existing variables defined u8 & u16 as well as to be consistent with
Zephyr naming conventions.
Jira: ZEP-2051
Change-Id: I451fed0623b029d65866622e478225dfab2c0ca8
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Fix doxygen comment typos used to generate API docs
Change-Id: I6fd5051c99bdcc731740c92001e525349c254d85
Signed-off-by: David B. Kinder <david.b.kinder@intel.com>
This reverts commit e60af3be66.
We revert this as we intent to move away from {u}int{8,16,32,64}_t types
to our own internal types for sized variables so we shouldn't need the
PRI macros anymore.
Change-Id: I4a57eb2c23cb1b137112224f604602d40c7cce4f
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
To allow for various libc implementations (like newlib) in which the way
various {u}int{8,16,32}_t types are defined vary between both libc
implementations and across architectures we need to utilize the PRI
defines.
Change-Id: I69e60e3823028389b314adaf6e279fd47fde1182
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Added serial (UART) driver for Atmel SAM MCU family.
Note:
- Error handling is not implemented
- The driver works only in polling mode, interrupt mode is
not implemented.
Tested on Atmel SMART SAM E70 Xplained board
Origin: Original
Jira: ZEP-1959
Change-Id: I3e770fd1feb2ddf92cf405a9aa17be92eb32e19b
Signed-off-by: Piotr Mienkowski <piotr.mienkowski@gmail.com>
Added I2C bus (TWIHS) driver for Atmel SAM MCU family. Only
I2C Master Mode with 7 bit addressing is currently supported.
Tested on Atmel SMART SAM E70 Xplained board
Origin: Original
Jira: ZEP-1866
Change-Id: Ic5aa7b6b21295feccae883d580b38bbeaf2ce291
Signed-off-by: Piotr Mienkowski <piotr.mienkowski@gmail.com>
Add plumbing to build system and SoC level dtsi for the NRF52832 SoC.
We additionally add the necessary yaml files for the UART on the NRF52
SoCs.
Change-Id: I3b4a821b2993827e33d8e84bdbbc759d1521f8bd
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
The MKL25Z soc do not support irqs in PORTB, PORTC and PORTE.
This is a patch to not enable irq if such ports are enabled.
Change-Id: I7b0b308504fcea47714fee8f2913baf336c4aa7d
Signed-off-by: Gustavo Denardin <gustavo.denardin@gmail.com>
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Now that all STM32 platforms are using device tree we can remove the
handling for !HAS_DTS from the serial driver.
Change-Id: Ifafc283f2509dd9a438f321e0b647720d4f13810
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Now that all NXP MCUX platforms are using device tree we can remove the
handling for !HAS_DTS from the serial drivers.
Change-Id: I05185142afa7fae83ce68de954202829868af88f
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Wrong base address has been provided to I2C_2 instance.
Fix this issue for proper behavior
Change-Id: I81e5cb71a5136e742f460db5db39b2adf2f10f2d
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
I2C_SHARED_IRQ, I2C_0_IRQ_SHARED, I2C_0_IRQ_DIRECT Kconfig options
are DW driver specific. Its presence is confusing for a user of any
other I2C driver than DW. This patch renames these options to include
DW string and makes it visible only for DW I2C driver. This is a
similar implementation to that used by ETH DW Ethernet driver.
Change-Id: I795506f9b103c028a22317df9ad632dce5cd1343
Signed-off-by: Piotr Mienkowski <piotr.mienkowski@gmail.com>
Add support for nRF5x series GPIOTE based PWM driver
implementation.
Provides upto 3 pins/channels using one HF timer, two PPI
channels per pin, and one GPIOTE config per pin.
Change-id: I6056b199ec2cff595ba8fea9f659a0338ed4635b
Signed-off-by: Vinayak Chettimada <vinayak.kariappa.chettimada@nordicsemi.no>
Correct the way interrupts are enabled and disabled using the INTENSET
and INTENCLR registers, which ignore all 0s written to them and are both
positive registers.
Change-Id: I052548b0255d9d5ae36b2a708ed1968ae3ab1d06
Signed-off-by: Carles Cufi <carles.cufi@nordicsemi.no>
simcall must be in the volatile asm so that gcc does not optimize it
out. It also needs "memory" clobber to make sure data passed through
memory buffer is actually written back before the simcall.
Change-Id: I410b7348bf605d0d08f81ec5395f6cb144f33a43
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Check net_recv_data() return value, if it returns an error release
the net_buf. Based on a fix in eth_mcux driver.
Change-Id: I44ca5fd8dfb7175620b7e8850a68443100039db6
Signed-off-by: Piotr Mienkowski <piotr.mienkowski@gmail.com>
Add the simplest possible CRC 16 function that computes the CRC value
without the help of lookup tables.
Change-Id: I9163389adaa4a70c4e8ce8ce6d5f0661f40c7871
Signed-off-by: Patrik Flykt <patrik.flykt@intel.com>
Check net_recv_data() return value and if it returns an error
then release the net_buf in order to avoid leaking it.
Coverity-CID: 158884
Change-Id: I10d411a2de4b7c7bbe2475df65d93f5b1e619679
Signed-off-by: Jukka Rissanen <jukka.rissanen@linux.intel.com>
CONFIG_* usually come from Kconfig, rename variables that are locally
defined to avoid confusion about where they are set.
Change-Id: I83b8459913c5deb68dc1b9f5386b8934363a6d1f
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
That option was not defined and the sensor does not have this feature,
probably was part of some copy/paste mistake.
Change-Id: Ib24d1f85cf90648b01fa81b285a1ec01fe28c545
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
The following warning occurs when !SYS_LOG_INF due to the fact
that these variables are only used for information purposes.
When logging is <INFO then the variables aren't utilised at all.
To fix this we're removing the variables completely and using
the direct calls from within the information prints instead.
drivers/dma/dma_stm32f4x.c: In function 'dma_stm32_dump_reg':
drivers/dma/dma_stm32f4x.c:196:11: warning: unused variable 'sfcr' [-Wunused-variable]
uint32_t sfcr = dma_stm32_read(ddata, DMA_STM32_SFCR(id));
^
drivers/dma/dma_stm32f4x.c:195:11: warning: unused variable 'sm1ar' [-Wunused-variable]
uint32_t sm1ar = dma_stm32_read(ddata, DMA_STM32_SM1AR(id));
^
drivers/dma/dma_stm32f4x.c:194:11: warning: unused variable 'sm0ar' [-Wunused-variable]
uint32_t sm0ar = dma_stm32_read(ddata, DMA_STM32_SM0AR(id));
^
drivers/dma/dma_stm32f4x.c:193:11: warning: unused variable 'spar' [-Wunused-variable]
uint32_t spar = dma_stm32_read(ddata, DMA_STM32_SPAR(id));
^
drivers/dma/dma_stm32f4x.c:192:11: warning: unused variable 'ndtr' [-Wunused-variable]
uint32_t ndtr = dma_stm32_read(ddata, DMA_STM32_SNDTR(id));
^
drivers/dma/dma_stm32f4x.c:191:11: warning: unused variable 'scr' [-Wunused-variable]
uint32_t scr = dma_stm32_read(ddata, DMA_STM32_SCR(id));
Change-Id: I91a0373ef6c9afa8a342181c0ab24bd58743300d
Signed-off-by: Lee Jones <lee.jones@linaro.org>
To follow Zephyr convention this patch is placing all I2C driver
Kconfig options in submenu.
Change-Id: Ibc485305b7effb65ed7f24b933fe35d0fa0afee8
Signed-off-by: Piotr Mienkowski <piotr.mienkowski@gmail.com>
I2C_CLOCK_SPEED Kconfig option is DW driver specific. It does not
define I2C interface speed but rather the I2C DW module clock speed.
It is confusing for a user of any other I2C driver than DW.
This patch renames this option to I2C_DW_CLOCK_SPEED and makes it
visible only for DW I2C driver.
Change-Id: I97f57332fd5cca644eabdef0968a0b2174b885ff
Signed-off-by: Piotr Mienkowski <piotr.mienkowski@gmail.com>
Atmel SAM family GMAC Ethernet driver is implementing zero-copy
networking. As a result it has to reserve a defined amount of RX
data net buffers before bringing up the interface. Since net buffer
pool is initialized by the network stack and this driver was bringing
the interface up in its initialization function the driver initialization
was performed, as a workaround, after network stack initialization. It
is not a clean solution. This patch fixes this by bringing the
interface up in interface initialization function. The driver itself
can now be initialized before the network stack is.
Tested on Atmel SMART SAM E70 Xplained board
Change-Id: I65886fd6db6f27a10628e393cfabd8e5f78c08ff
Signed-off-by: Piotr Mienkowski <piotr.mienkowski@gmail.com>
Fix eth_tx function which was dereferencing a pointer before
checking that it is not null.
Tested on Atmel SMART SAM E70 Xplained board
Change-Id: Idae4cf9d9a80f6ee9f74a94dd1debe7511c5fab4
Signed-off-by: Piotr Mienkowski <piotr.mienkowski@gmail.com>
Adds basic sensor driver support for the Maxim MAX30101 heart rate
sensor.
This driver does not yet support any sensor triggers such as the data
ready trigger, or runtime changing of sensor attributes.
Default configuration values were taken from the MikroE Hexiwear driver.
https://github.com/MikroElektronika/HEXIWEAR
Datasheet: https://datasheets.maximintegrated.com/en/ds/MAX30101.pdf
Jira: ZEP-720
Change-Id: Ie8981e124da36a56a214f133bf9a11b9f47d60fa
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
Both the string and image rendering may want to take advantage of
scrolling and sequential display capabilities. Consolidate the APIs so
that there's a single one for images (mb_display_image) and a single
one for strings (mb_display_print). Both take a duration parameter for
the per-frame duration as well as a mode parameter which specifies
sequential vs scrolling behavior as well as an optional looping flag.
Change-Id: Ia092d771e3f1b94afd494c7544dab988161c539e
Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
Reorder the struct members for more compact layout. The current row
tracker tracks just values 0 to 2 so uint8_t is more than enough for
it.
Change-Id: I845c84aeb32d59ed0ebbd55d8b6cfda7ad19b75a
Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
We don't need to store copies of the current and next image when
scrolling text, since looking up the font is just as efficient and
also consumes less memory.
Change-Id: Ia905164c5b5784afb52cb2bb38c1ab1d00817df0
Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
Add a helper function to reset the state of the display, and make use
of it from the various public functions. This also ensures that the
timer is stopped before starting a new display routine.
Change-Id: I8a916b5b13c18b41b7fc3593e6d97e874ef117af
Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
Add an empty column between characters of scrolling text so that the
individual characters are more easily distinguishable instead of being
back-to-back mashed together.
Also adjust the default scrolling step interval so that the character
display frequency stays roughly the same as before.
Change-Id: Idca0dc149a84f3f99b753a28ad1120ce75b97667
Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
For a better clarity and minimize the possibility
of false definitions and duplicates, gather defines
by port and store the by alphabetical order then in
alternate function order.
Change-Id: Ib9febc9e6c5037a774190007120b87bf100c3fca
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
* SPIMx support for nrf52 spi interface with easy dma
Change-Id: I3221b14867924b91a9d809faf689090574f5dc1c
Signed-off-by: Roger Lendenmann <roger.lendenmann@intel.com>
Add support for I2C_2 instance on stm32lx driver
Change-Id: Iaa17305dd21f92954274ca522d30d464e0a53b7b
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
It is envisaged that this will be used by SoC or board code to make
available fixed purpose memory-mapped i/o registers to the rest of the
system which normally expects to use GPIO devices, e.g. for driving chip
select lines, LEDs or reading button states.
As such, the driver code doesn't provide a kconfig based configuration
mechanism, instead SoC/board code can hard-wire the devices it wants
with something simple like:
GPIO_MMIO32_INIT(misc_reg1, "MISC1", 0x12345678, 0xffffffffu)
Then, for example, if bit N of the register at 0x12345678 is wired up as
an SPI device chip select line, the SPI driver could be configured to
use pin N of the "MISC1" GPIO driver and not need any other board
specific code.
Change-Id: Ib02fcbab73fcf9637e25834db060fb3108626f47
Signed-off-by: Jon Medhurst <tixy@linaro.org>
On stm32 family, IP instance numbering starts from 1.
Update i2c driver to this scheme to minimize user
confusion
Change-Id: I967d5975bbbad59cd8a3a7b6dfc665955d09cc9f
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
As part of the transition to Device Tree, a temporary
HAS_DTS configuration variable, and a .fixup file per board
with symbol aliases were added.
This patch removes the cc32xx related fixup file
definitions, except for those used additionally outside
the cc32xx drivers.
Since cc32xx has DTS files, and since HAS_DTS will always be true,
it also removes the 'if !HAS_DTS' blocks from the cc32xx Kconfig
files.
Change-Id: I1c1b9f734795f523342f82ab32f2a38983812c0b
Signed-off-by: Gil Pitney <gil.pitney@linaro.org>
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Previously, cc3200_launchxl board was not able to show the
Zephyr Boot Banner, as that required early initialization
of the UART driver, which was done POST_KERNEL.
This patch moves the pinmux and UART driver initialization
to PRE_KERNEL_1, allowing early printk, and the Boot Banner
to show.
Change-Id: I84a7c20c1d5bdc3de150dc6bb0adebc9a2d9f5cb
Signed-off-by: Gil Pitney <gil.pitney@linaro.org>
Add a new mb_display_print() API which takes printf-style parameters
and outputs scrolling text instead of one character at a time. The
existing mb_display_str() API is renamed to mb_display_string() for
consistency, and now also takes printf-style parameters.
Change-Id: I59c42bcd74c62f05ecb6d097dc808b9e5c1984c5
Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
Adds a simple driver to access the 5x5 LED display found on BBC
micro:bit boards. The display is so limited that no effort is done to
try to integrate with the existing console (which would likely make
the display unusable). Instead, dedicated mb_display_* APIs are added
that are specific to this display.
References:
https://www.microbit.co.uk/device/screenhttps://lancaster-university.github.io/microbit-docs/ubit/display/
Jira: ZEP-1990
Change-Id: I431b5b358b5f07592a60d3aed87eaab6ac20ce25
Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
The SiFive Freedom E310 Platform Level Interrupt Controller (PLIC) follows
the riscv PLIC specification as defined in the riscv privilege
architecture specification.
It provides implementation for the riscv PLIC APIs as
required by the riscv-privilege SOC Family for SOCs providing
support for the RISCV_HAS_PLIC config.
Change-Id: I95d02edb53deeccd91e490776e8e1dbfb82d235f
Signed-off-by: Jean-Paul Etienne <fractalclone@gmail.com>
Rearming the riscv machine timer is done by first updating the
mtimecmp low value register. If the low value is updated with a
relatively small value, a timer interrupt can be generated while
updating the mtimecmp high value.
To avoid such a spurious interrupt to occur, disable the timer
interrupt while rearming the timer.
Change-Id: I50ab3f19554a9a8dfe70943b6da0d20be3de88dc
Signed-off-by: Jean-Paul Etienne <fractalclone@gmail.com>
This will provide the feature through Crypto API.
Change-Id: If6953a54b393544b019755ae73571effe0724e69
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
Without this bit set, if we a pass ptr to a string such as:
"This is a string\n"
The DMA'ed output would be:
"TTTTTTTTTTTTTTTTTT"
Change-Id: I0186c95ddca0390596d22af2551dbfa6716a5082
Signed-off-by: Lee Jones <lee.jones@linaro.org>
The device data structure is statically declared and referenced
on a per-controller basis during driver registration. Unfortunately,
due to using the same name (ddata) to initially declare as used
in individual functions, we accidentally referenced the main struct
by mistake due to a lack of local declaration. Let's prevent that
from happening again by using different name-spaces.
Change-Id: I9f7e5e7f95ee68d71aee70fa979e015ca2b5519e
Signed-off-by: Lee Jones <lee.jones@linaro.org>
The STM32 DMA controller supplies streams, which in turn provide a
selection of channels. The stream number is provided by the DMA API
through it's 'channel' argument, but the sub-channel (within the
stream) is specified on an application case by case bases via Kconfig.
Change-Id: Ib5bfdb80f4d616516850787e1402164807771c5e
Signed-off-by: Lee Jones <lee.jones@linaro.org>
Some controllers contain channels with-in channels, or in the case
of the STM32 DMA controller channels within streams. Channels
will vary depending on application, so these need to be provided
on a use-case bases.
Change-Id: I4f5fe3ec5817583b95dc7f059b5dc57f937523c4
Signed-off-by: Lee Jones <lee.jones@linaro.org>
Fixes the fxos8700 Kconfig help indentation to be <tab><space><space>.
Change-Id: If6e9395b5d28044962ca568be5515658e7dc2627
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
Adds sensor driver support for the NXP FXAS21002 3-axis gyroscope.
Includes statically configurable range and output data rate, as well as
the sensor data ready trigger.
Datasheet:
http://www.nxp.com/assets/documents/data/en/data-sheets/FXAS21002.pdf
Jira: ZEP-1392
Change-Id: I84587c4d5e76863245e9d045c6abb10b21b2615a
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
Each controller contains a number of streams. Subsequently each
stream contains a number of channels. Channels are selectable
via the stream's control register.
Change-Id: Ib75d1377cb8fc38f27e4566b275343b2ffb8da65
Signed-off-by: Lee Jones <lee.jones@linaro.org>
Commit c0bd8a0ce4 ("api: dma: dma api update") introduced some new APIs
and deprecated the old ones. Let's move to the new API before the old
calls are completely removed.
Change-Id: I21795fa20124f8101c56b0fceb0f0d9afd96b0f0
Signed-off-by: Lee Jones <lee.jones@linaro.org>
File include/misc/sys_log.h has been moved to include/logging/sys_log.h.
Change-Id: I011ca632396b574ae7e388b47fc2ba3a58fafc7b
Signed-off-by: Lee Jones <lee.jones@linaro.org>
Providing a new line, then an attribute on the same line as the
following closing bracket is odd. Move to something more
transitional and in line with regular coding standards.
Change-Id: I08f7cd76ca2f522a8b5b6de2e5baf94e95b5195a
Signed-off-by: Lee Jones <lee.jones@linaro.org>
It is possible to evaluate the TXE bit *before* H/W has had the
opportunity to detect that data is being processed. Therefore
we should hold off on any evaluation until TXE has initially been
set.
Change-Id: Iff26bfbe3ab419734003bf81a4cb357de83908e7
Signed-off-by: Lee Jones <lee.jones@linaro.org>
Currently only 1 is allowed. While we're at it, let's generify the
existing entries, since they could be used by all controllers, not
just QMSI.
Change-Id: Iec5d195fff239931b21a7584eb4b642b40f95be5
Signed-off-by: Lee Jones <lee.jones@linaro.org>
Currently the entries for STM32 UART ports are at the same level than
the top menuconfig UART_STM32. As a result they are mixed with other
configs in the "Serial Drivers" menu.
Use if/endif grammar to put these entries under a dedicated STM32
submenu.
Change-Id: If28945204b801578d29f8cce7c2370ca3c2737a1
Signed-off-by: Florian Vaussard <florian.vaussard@heig-vd.ch>
Add support for GPIO banks I to K that can be found on some high-density
STM32F4 products.
Change-Id: I2cb65ed4d4a2282f7d17478cb1fcdd65dffe71b0
Signed-off-by: Florian Vaussard <florian.vaussard@heig-vd.ch>
The registration of each GPIO bank differs by only few details. These
differences can be factorized in order to create a generic registration
macro.
This has several advantages:
- Less code
- Easier to add new banks
- Less work to add support for new STM32 families
The diff stat speaks for it-self: 26 insertions(+), 92 deletions(-)
Change-Id: I674752fda5ee3caefb815ccf070a1b636b16cf85
Signed-off-by: Florian Vaussard <florian.vaussard@heig-vd.ch>
The PLLN multiplier can range between 50 and 432 on all STM32F4, except
on the STM32F401 where the lower bound is restricted to 192.
Fix the range property and the help text to reflect this reality.
Change-Id: I7b93e84b321f7869aaf611287344cd3e25c893c8
Signed-off-by: Florian Vaussard <florian.vaussard@heig-vd.ch>
Since all interrupts come in on the status line,
we only connect it for the KL2X.
Change-Id: Ia9e0d483fe68464a0eeab08c95a043260e5793b0
Signed-off-by: Gustavo Denardin <gustavo.denardin@gmail.com>
Clear pending IRQ when starting and restore back the RTC1 state when
disabling sys_clock, to avoid issues when soft rebooting the device or
chainloading another Zephyr image (e.g. mcuboot).
Change-Id: I693d9168196ad2cfb8475ecfa2051eac043b1fbd
Signed-off-by: Ricardo Salveti <ricardo.salveti@linaro.org>
In prep for supporting the older KL2x SoCs that use a different SPI
block, rename the current SPI driver to DSPI to match what the MCUX HAL
defines it as.
Change-Id: I9097580df5fca649ab6fd9a38212fced0b1ea6ed
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
At the moment CC2520 configuration options are selected inside "TI
CC2520 Driver RAW channe" submenu like:
[*] TI CC2520 Driver support ----
[ ] TI CC2520 Driver RAW channel --->
Make RAW channel depends on TI CC2520.
Change-Id: I92879b7f4391f1842c012b6c03c78956e90b9441
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
The fxos8700 is primarily an accelerometer/magnetometer, but it does
also include a temperature sensor. Note that the temperature sensor is
uncalibrated and can only be used when the magnetometer is enabled
(magnetometer-only mode or hybrid mode).
Change-Id: I74c4ae68c30e0f9836caa70baed44ad8956b17ea
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
Declaring these as const lets the linker generate more optimal code.
Some extra care is needed with hci_ecc.c since it was overwriting the
send callback. Now the choice of send() call is done directly in the
bt_send() function
Change-Id: Iac74f5ee9bee097bbb34c11bd13d1d886700f5cc
Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
Support connection via SPI and keep I2C as the default.
Jira: ZEP-1698
Change-Id: I42a76131577a37429375364deb07e451107f5d81
Signed-off-by: Dario Pennisi <dario@iptronix.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Allow user to set the four last bytes of a MAC address.
By default the bytes are selected randomly but for testing
purposes we need a way to specify the address in advance.
Change-Id: Ic9820a8026b327d1ee5025ab77fdc77f5778de67
Signed-off-by: Jukka Rissanen <jukka.rissanen@linux.intel.com>
Networking stack has split one global DATA pool to RX and TX DATA pools
and also added net_buf pool support to each context. Update the driver
to support this new design. Since the GMAC TX descriptor list has a fixed
size but the number of TX DATA buffers is no longer limited updating the
TX descriptor list has to be guarded by a semaphore.
Tested on Atmel SMART SAM E70 Xplained board
Change-Id: I181e1cdd183e173b85d5d1711b6e78cd5165666d
Signed-off-by: Piotr Mienkowski <piotr.mienkowski@gmail.com>
It is possible that the slip->last pointer is not set during
the startup of the slip driver if we receive some garbage bytes.
This in turn caused memory to be overwritten in random places.
Jira: ZEP-1737
Change-Id: Ia2ce193b81a8f707b7ca63497d497ea70699bb32
Signed-off-by: Jukka Rissanen <jukka.rissanen@linux.intel.com>
No need to always look through all the network interfaces
when receiving packet as we support only one interface and
it is always the same one.
Change-Id: Ic0bfabc8409160352081cac1a6c3dbbfa35fe390
Signed-off-by: Jukka Rissanen <jukka.rissanen@linux.intel.com>
The current state of affairs will not allow to set a MAC address and
thus will initialize a random MAC address.
However, when we are in a situation where we are trying to interface
Zephyr OS QEMU VMs with physical targets for testing, this is not
practical. We need to create a macvtap interface, on which we need to
set the MAC address of the Zephyr OS SLIP device so packets can be
routed. There is no way to guess which random address is going to be
used, and there is no practical way to query it.
So this patch adds a CONFIG_SLIP_MAC_ADDR config
setting. slip_iface_init() is changed to take the code from
slip_get_mac() for initializing the MAC address (which should be
happening there anyway) and if CONFIG_SLIP_MAC_ADDR is set, it takes
that one -- otherwise goes to generate a random one.
Change-Id: I55a68f2743604f310d41c934783eca82084d7e94
Signed-off-by: Inaky Perez-Gonzalez <inaky.perez-gonzalez@intel.com>
Add few nop instructions to allow the DMA controller settle,
It takes time after starting the transfer to access the DMA
controller registers, so a few cycles are added, the minimal number
of cycles needed has been calculated using tests results on c1000
development board.
Jira: ZEP-1803
Change-Id: I1f8e8478f0350e1b6e4dd596b783dc4babc2d02b
Signed-off-by: Sergio Rodriguez <sergio.sf.rodriguez@intel.com>
This commit adds missing RAW mode device to the driver.
Change-Id: I9ee9c41bc94b0ae202613ef707030033b46df1de
Signed-off-by: Wojciech Bober <wojciech.bober@nordicsemi.no>
The PHY debug code is useful while working specifically with the PHY
state machine, but in general the frequent, periodic nature of the
output is a hinderance. Turn down the verbosity, leave a local define
available for anyone who specifically needs to see the PHY state
machine debug.
Change-Id: I40e59b6df5c29702813d3a554ea9e795a3761c65
Signed-off-by: Marcus Shawcroft <marcus.shawcroft@arm.com>
The enc28j60's reception routine requires a timeout
for a buffer assignation. The timeout is configurable
to allow a per application fine tuning.
The effect that K_NO_WAIT currently has is that there are frames
lost everytime that a buffer is required and there are none
available.
Jira: ZEP-1169
Change-Id: Ia18736fd85daee51fe1c2304977209cc7f0038b5
Signed-off-by: Juan Manuel Cruz <juan.m.cruz.alcaraz@intel.com>
The code used net_nbuf_get_reserve_{rx|tx}_data() function to
allocate a fragment. Instead of that low level function, use
net_nbuf_get_frag() instead. There are few places this is not
possible or is too big change like in few test programs.
Change-Id: Ied7e2b7db352de998b200ffa6ff82471bfa5ebe3
Signed-off-by: Jukka Rissanen <jukka.rissanen@linux.intel.com>
If we receive lot of packets, it might happen that we exhaust
all the DATA buffers in the system. This would prevent from
us sending anything to the network.
Change this by splitting the DATA buffer pool into RX and TX
parts. This way RX flooding cannot consume all DATA buffers
that needs to be sent.
Change-Id: I8e8934c6d5fdd47b579ffa6268721b5eb3d64b6d
Signed-off-by: Jukka Rissanen <jukka.rissanen@linux.intel.com>
Provide a configuration option for promiscuous mode.
Promiscuous mode provides a convenient workaround for ZEP-1673 however
it generates significant demand for RX buffers on a loaded network.
Add a configuration option to conveniently enable / disable.
The Kconfig defaults promiscuous on to workaroudn 1673, once that
issue is resolved the default logic on NET_IPV6 will be dropped.
Change-Id: I6929aca70d7bd88ce88c65d6654d664ea6653b66
Signed-off-by: Marcus Shawcroft <marcus.shawcroft@arm.com>
Basic Watchdog driver for Atmel SAM family MCUs. Currently only
disabling the watchdog is supported.
Tested on Atmel SAMV71 Xplained Ultra Evaluation Kit.
Origin: Original
Jira: ZEP-1684
Change-Id: I8f717c7f53aa290c944b7935e0570c2a6f53956e
Signed-off-by: Souvik K Chakravarty <souvik.k.chakravarty@intel.com>
Provide a random driver wrapped around the MCUX TRNG driver.
Change-Id: Icbd7ab587aa18ecbd7eae52290aaa5d8ee504cf2
Origin: Original
Signed-off-by: Bogdan Davidoaia <bogdan.davidoaia@linaro.org>
MCUX contains more than one type of random number generator,
so refrect this in config and file names.
Change-Id: Iba4482a1ae41f35d471686f8b159c113147c4df8
Signed-off-by: Bogdan Davidoaia <bogdan.davidoaia@linaro.org>
Current users of sys_bitfield*() are bending over backwards to cast
what is most of the times a pointer into an integer.
Bitfields can be better described with an void *, so
uint{8,16,32,64}_t or any other container can be used. Most
sys_bitfield*() operations, by extension, can do the same. Note void *
has byte arithmetic, like char *.
This change will also make it implicit, for any future split of the
address space between virtual (what the SW is seeing) and physical
(what the HW is seeing) way clearer, as the functions dealing with
physical, non directly referentiable/mappeable addreses to use an
integer type, like mem_addr_t.
- include/arch/ARCH/*asm_inline*:
- sys_bitfield*() all modified to take 'void *'
Note 'void *' arihtmethic is byte based, which makes some things
easier.
- include/sys_io.h:
- introduces DEFINE_BITFIELD
- update docs
- tests/kernel/bitfield: remove all the cast contortions, use DEFINE_BITFIELD
PENDING: update other TCs
- include/arch/nios/nios2.h, drivers/interrupt_controller/ioapic_intr.c:
remove cast contortions
Change-Id: I901e62c76af46f26ff0d29cdc37099597f884511
Jira: ZEP-1347
Signed-off-by: Inaky Perez-Gonzalez <inaky.perez-gonzalez@intel.com>
These are more consistent with naming used by other ports (uppercase,
short), and some existing software relies on them to be exactly those.
This change is a follow up to the discussion on the Zephyr mailing
list, calling to establish consistent naming conventions for Zephyr
devices, and is a small step in that direction.
Change-Id: I013b0505b579c6337aeb6fbef2423216ca6cf046
Signed-off-by: Paul Sokolovsky <paul.sokolovsky@linaro.org>
To secure correct signal levels on the pins by the UART when
the system is in OFF mode, the pins must be configured in
the GPIO peripheral as described in nRF5 Product
Specification.
UART Pin, Direction, Output Value:
RXD, Input, NA
CTS, Input, NA
RTS, Output, 1
TX, Output, 1
This commit sets the RTS line to a initial value of 1.
Change-id: I5147fe58033f42c979b9354798b6fd13d78f7f71
Signed-off-by: Vinayak Chettimada <vinayak.kariappa.chettimada@nordicsemi.no>
To avoid glitches in the lines, set the line to the pull specified
before actually changing the line's direction (in/out) so that no
unexpected pulses are generated.
Change-id: I4fe133c5b82f2a1bfa473341612c2c7eca9027b8
Signed-off-by: Krzysztof Chruściński <Krzysztof.Chruscinski@nordicsemi.no>
Signed-off-by: Carles Cufi <carles.cufi@nordicsemi.no>
Signed-off-by: Vinayak Chettimada <vinayak.kariappa.chettimada@nordicsemi.no>
Refactor the PHY state machine and add support for explicit start and
stop.
The stop implementation remains partial, the state machine will enter
a disabled state but will not actual attempt to power down the PHY.
This is deliberate, while implementing this it has become apparent
that issuing a PHY power down command is an effective way of bricking
frdm-k64f boards, hence explicit power down deliberately disabled
until the issue is properly understood.
Change-Id: I846a51b0ac48feed35d260cf20b50f4f1ac59298
Signed-off-by: Marcus Shawcroft <marcus.shawcroft@arm.com>
Add the link type to net_if_set_link_addr() call. This fixes the
driver after changes introduced in
4eb2020055.
Change-Id: I72475a055ac805524b4b0f0c2380513e8f041368
Signed-off-by: Wojciech Bober <wojciech.bober@nordicsemi.no>
Some fixes where needed to get PLL2 source of PREVI1 functional.
Compiled ok with following configuration:
CONFIG_CLOCK_STM32F10X_CONN_LINE_PREDIV1_SRC_PLL2CLK=y
CONFIG_CLOCK_STM32F10X_CONN_LINE_PREDIV2=0
CONFIG_CLOCK_STM32F10X_CONN_LINE_PLL2_MULTIPLIER=8
Jira: ZEP-1758
Change-Id: I5ddfaef1b44c4c4e5e6adedc158a1c9092bc8df5
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Some GPIO ports activation where missing since not used
on available soc/boards.
Since stm32 family increases, activation of these ports
should be made available.
Jira: ZEP-1551
Change-Id: I612d135b28ef255bc771599e33796671ff81d0ac
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
We need to account for the interrupt happening in the middle
of the calculation.
Issue: ZEP-1546
Change-Id: I193534856d7521cac7ca354d3e5b65e93b984bb1
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Using net_nbuf_unref to release the net_buf so that we can
debug the allocations more easily. It is ok to use the original
net_buf_unref() too, we just miss some important net_buf
housekeeping information if done like that.
Change-Id: Ieb7b39ed525bfc46eb5c07a01f2a3a75fdbeb9fd
Signed-off-by: Jukka Rissanen <jukka.rissanen@linux.intel.com>
If slip_input_byte fails to get buffer for the first byte then no point
of saving later bytes and send it to upper layers. Final packet will be
incomplete and upper layers will discard it. Consider incoming bytes
only after successful buffer allocation on first byte, otherwise silently
ignore it.
Change-Id: Ie16d0df0c608d1644d39f66900252a340051c012
Signed-off-by: Ravi kumar Veeramally <ravikumar.veeramally@linux.intel.com>
No functionality changes. Added more comments and used switch cases
for more readability.
Change-Id: I9396270d7368d9b0c923a88f90b44129a1d69cbc
Signed-off-by: Ravi kumar Veeramally <ravikumar.veeramally@linux.intel.com>
The interface L2 address type is set at the same time as the
L2 address is set to the network interface. This is most
convinient place to set the address type.
Change-Id: I712d7357d075959eb79df3463141cfbc6d163a74
Signed-off-by: Jukka Rissanen <jukka.rissanen@linux.intel.com>
This commit adds a driver for nRF5 802.15.4 radio. This driver
is a wrapper for the driver provided by ext/hal/nordic/drivers.
Change-Id: I20ee4aff3d1b994c621ba8eaab208d15d85e4c01
Signed-off-by: Wojciech Bober <wojciech.bober@nordicsemi.no>
The interrupt processing of MCR20A was flawed and complicated.
This patch simplifies the handling of interrupts and reduces
the number of necessary SPI transfers.
Minor fixes:
- use mutex for the PHY access control
- remove unnecessary mcr20a_mask_irqb calls
- do not read RX_FRM_LEN twice
- increase timeout for sequence synchronization semaphore
if the log level greater than 1
- enable only the Sequence-end (SEQIRQ) interrupt
- fix magic in NET_DEVICE_INIT
- make the timeout values dependent on the log level
Change-Id: Ib3f64a092ffba91c80ff6e1d5cec995ab9d40bfb
Signed-off-by: Johann Fischer <j.fischer@phytec.de>
Fixes an unlikely issue that could arise if the RTC handler in the nRF RTC
driver was blocked for more than one sys tick interval. This could lead to
_sys_clock_tick_announce() being called with more than one sys tick when the
kernel did not expect it.
Jira: ZEP-1763
Change-ID: I5608fca6f0ac97a17c1ce452c1c5c67696a49a9a
Signed-off-by: Øyvind Hovdsveen <oyvind.hovdsveen@nordicsemi.no>
The LOAPIC driver was doing this in a way susceptible to a very
nasty race condition: the CCR register could reset and be readable
before the associated interrupt could be delivered.
This resulted in a small window of time where CCR was reset, but
accumulated_cycle_count not updated, causing some calls to
k_cycle_get_32() to appear to jump backwards in time.
Just use the x86 TSC for these cycle timestamps. A divisor may be
provided in cases where the CPU clock speed is some multiple of
the bus speed. Modern x86 CPUs do not change their TSC rate even
when adjusting cpu frequency, so this should be a reliable timing
source.
Issue: ZEP-1546
Change-Id: I441bd8e32af866587a91f306e89e3fa0ece512b5
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
It's possible the timer interrupt could occur when performing the
computation, resulting in incorrect values returned.
It's still possible for bad values to be returned if the function is
called with interrupts locked, but that is only fixable with a second
timer source.
Issue: ZEP-1546
Change-Id: I16d5b04c3e32377f7249eb4fb1bf2f7c22bd0836
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Some files made it through review process with full license header.
Change-Id: I2722b127c40b4b19500042c12e4fde85a165bae9
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
This is a reworked version of the previous RTC driver. The main
changed is related to the handling _timer_idle_exit() on non-RTC
wake-ups. The previous version didn't announce the elapsed time
to the kernel in _timer_idle_exit(). Additionally, the driver now
makes sure never to announce more idle ticks than the kernel asked
for, since the kernel does not handle negative deltas in its timeout
queues.
Change-Id: I312a357a7ce8f0c22adf5153731064b92870e47e
Signed-off-by: Wojciech Bober <wojciech.bober@nordicsemi.no>
Signed-off-by: Øyvind Hovdsveen <oyvind.hovdsveen@nordicsemi.no>
Signed-off-by: Carles Cufi <carles.cufi@nordicsemi.no>
Some arches may want to define this as an inline function, or
define in core arch code instead of timer driver code.
Unfortunately, this means we need to remove from the footprint
tests, but this is not typically a large function.
Issue: ZEP-1546
Change-Id: Ic0d7a33507da855995838f4703d872cd613a2ca2
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
On Nios II the same timer peripheral IP block can't function
as a periodic system timer and a high-resolution timestamp source.
A second timer instance with different configuration is required.
Until that is implemented, just return the accumulated cycle count.
Issue: ZEP-1546
Change-Id: If3dcebdc60334bf3aa0ab45ccd82f1b2531b6bc1
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
There are race conditions trying to coordinate the value between
the accumulated_cycle_count (updated at interrupt time) and
trying to compute the delta from the last interrupt using the
mtime registers. An unlucky call could result in the timestamp
appearing to move backwards in time.
the 'mtime' register isn't reset at every interrupt. Since we just
want a cycle counter, report its raw value.
Issue: ZEP-1546
Change-Id: I9f404b33214d6502fea47374fcf0ecbf84ef8136
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
This driver currently only handles memory-to-memory transfers.
TODO: Add support for all types of transfers.
Change-Id: Ic9787dcca919a58fb11b48c9f6b6b371db88c3ea
Origin: Original
Maintained-by: Zephyr
Signed-off-by: Lee Jones <lee.jones@linaro.org>
Adds a driver for Atmel Crypto Authorization solution
ATAES132A crypto device.
The driver supports the following functionality.
- AES CCM encryption, decryption and authentication
- AES ECB block operation.
The driver requires an I2C device to access crypto device registers.
Jira: ZEP-1387
Change-Id: I60aa8f3b069b703d4f83d866d28391625bb9ac13
Signed-off-by: Juan Manuel Cruz Alcaraz <juan.m.cruz.alcaraz@intel.com>
Shim layer interfacing between crypto APIs and TinyCrypt
library. Currently facilitates only a subset of TinyCrypt
features/algorithms.
Jira: ZEP-509
Change-Id: I7fe6b9d86df016d92d717378d08a1ab09caafb31
Signed-off-by: Jithu Joseph <jithu.joseph@intel.com>
When a GPIO pin is configured, the shim driver will first read the
current values in the controller registers to keep the other pins from
changing their configuration. After that it sets the bits for the
corresponding pin accordingly.
When the flag to enable interrupts is passed to the function, the
corresponding bits are all set properly, but no changes are made if
interrupts are not requested. This makes it impossible to disable
interrupts for a given pin once they've been enabled.
Fix it by always resetting the interrupt enabled bit when they have not
been requested. Other values can be left untouched as they won't have
any effect.
Jira: ZEP-1717
Change-Id: I30e97bb06d966291e23d0c66ddf39bce615c287b
Signed-off-by: Iván Briano <ivan.briano@intel.com>
Requesting a flash_write with a length of 0 results in a flash
position being written. Instead we should return 0 unless there is
some other input parameter that is invalid.
Change-Id: Ife6e6e2314bbee2bde7d0b69db3122ca00c361e0
Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
This is a workaround for lack of driver API support for multicast
management. So, instead we want to receive all multicast frames
"by default", or otherwise basic IPv6 features, like address
resolution, don't work. On Kinetis Ethernet controller, that
translates to enabling promiscuous mode. The real fix depends
on ZEP-1673.
Change-Id: I98a27584be65bdc405de005383eb30bad2a7fcfc
Signed-off-by: Paul Sokolovsky <paul.sokolovsky@linaro.org>
Add basic PHY management sufficient to detect link up, link down and
auto negotiated link speed / duplex. The PHY driver is implemented as
a state machine that executed in the system work queue. The
implementation is non blocking, using the MII interrupt to capture the
completion of read and write events.
This PHY management should be fairly generic. In the future, it may be
beneficial to pull this code out as a standalone PHY driver for use
with other ethernet drivers.
JIRA: ZEP-1674
Change-Id: I3dcb5c14982ef4b40591fcf10d84840b8a2558e5
Signed-off-by: Marcus Shawcroft <marcus.shawcroft@arm.com>
This driver was written for v1.5 before the introduction of the function
_sys_clock_final_tick_announce. At that time _sys_idle_elapsed_ticks was reset
to 0 automatically. Now that it is reset by the new function, the driver needed
to be fixed.
Change-Id: I039b4dbacb691aaf992b37e44404abd19a54a833
Signed-off-by: Mazen NEIFER <mazen@nestwave.com>
This is needed by next commit as some assembly files handling interrupts use
some options from this file.
This file is not included in next commit to separate code and build system
aptches.
Change-Id: Iff3a8019362599beb0c0058c3169480fa5183c1c
Signed-off-by: Mazen NEIFER <mazen@nestwave.com>
These were reported by ISSM compiler.
Jira: ZEP-1179
Change-Id: I10d04c2949ad2a390d4c1159d2342c73108a58b7
Signed-off-by: Jithu Joseph <jithu.joseph@intel.com>
This commit brings code size optimization as suggested by Christer
Weinigel review during review of initial commit for this driver.
It also cleans up useless definition in header file.
Change-Id: Ibeaa2e51570dff21825c60c30ba83d939b31d938
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
After activation of cube based driver support on L4 and F3 series,
this commits performs the clean up of F3 and L4 relative code to
native clock control drivers.
Indirectly, it makes pwm driver supported de facto on F3 series
Change-Id: Idac17103a9b5ef6eab540719343cc8f5865f15fa
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
After introduction and activation of STM32Cube LL based driver on
F3 and L4 series, this commit removes the no more needed code for
native driver for these soc.
Change-Id: I266d1a3fc4b464cee34b1cc1a1a333c5bf923e41
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
After introducing STM32Cube based clock control driver for
stm32 family, update stm32f3xx flash driver to support it.
Clean up will be done afterwards.
Change-Id: I3260bb063f714fa29adbc71d8036f20479a99b34
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
