Correct the way interrupts are enabled and disabled using the INTENSET
and INTENCLR registers, which ignore all 0s written to them and are both
positive registers.
Change-Id: I052548b0255d9d5ae36b2a708ed1968ae3ab1d06
Signed-off-by: Carles Cufi <carles.cufi@nordicsemi.no>
It is envisaged that this will be used by SoC or board code to make
available fixed purpose memory-mapped i/o registers to the rest of the
system which normally expects to use GPIO devices, e.g. for driving chip
select lines, LEDs or reading button states.
As such, the driver code doesn't provide a kconfig based configuration
mechanism, instead SoC/board code can hard-wire the devices it wants
with something simple like:
GPIO_MMIO32_INIT(misc_reg1, "MISC1", 0x12345678, 0xffffffffu)
Then, for example, if bit N of the register at 0x12345678 is wired up as
an SPI device chip select line, the SPI driver could be configured to
use pin N of the "MISC1" GPIO driver and not need any other board
specific code.
Change-Id: Ib02fcbab73fcf9637e25834db060fb3108626f47
Signed-off-by: Jon Medhurst <tixy@linaro.org>
Add support for GPIO banks I to K that can be found on some high-density
STM32F4 products.
Change-Id: I2cb65ed4d4a2282f7d17478cb1fcdd65dffe71b0
Signed-off-by: Florian Vaussard <florian.vaussard@heig-vd.ch>
The registration of each GPIO bank differs by only few details. These
differences can be factorized in order to create a generic registration
macro.
This has several advantages:
- Less code
- Easier to add new banks
- Less work to add support for new STM32 families
The diff stat speaks for it-self: 26 insertions(+), 92 deletions(-)
Change-Id: I674752fda5ee3caefb815ccf070a1b636b16cf85
Signed-off-by: Florian Vaussard <florian.vaussard@heig-vd.ch>
These are more consistent with naming used by other ports (uppercase,
short), and some existing software relies on them to be exactly those.
This change is a follow up to the discussion on the Zephyr mailing
list, calling to establish consistent naming conventions for Zephyr
devices, and is a small step in that direction.
Change-Id: I013b0505b579c6337aeb6fbef2423216ca6cf046
Signed-off-by: Paul Sokolovsky <paul.sokolovsky@linaro.org>
To avoid glitches in the lines, set the line to the pull specified
before actually changing the line's direction (in/out) so that no
unexpected pulses are generated.
Change-id: I4fe133c5b82f2a1bfa473341612c2c7eca9027b8
Signed-off-by: Krzysztof Chruściński <Krzysztof.Chruscinski@nordicsemi.no>
Signed-off-by: Carles Cufi <carles.cufi@nordicsemi.no>
Signed-off-by: Vinayak Chettimada <vinayak.kariappa.chettimada@nordicsemi.no>
Some GPIO ports activation where missing since not used
on available soc/boards.
Since stm32 family increases, activation of these ports
should be made available.
Jira: ZEP-1551
Change-Id: I612d135b28ef255bc771599e33796671ff81d0ac
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
When a GPIO pin is configured, the shim driver will first read the
current values in the controller registers to keep the other pins from
changing their configuration. After that it sets the bits for the
corresponding pin accordingly.
When the flag to enable interrupts is passed to the function, the
corresponding bits are all set properly, but no changes are made if
interrupts are not requested. This makes it impossible to disable
interrupts for a given pin once they've been enabled.
Fix it by always resetting the interrupt enabled bit when they have not
been requested. Other values can be left untouched as they won't have
any effect.
Jira: ZEP-1717
Change-Id: I30e97bb06d966291e23d0c66ddf39bce615c287b
Signed-off-by: Iván Briano <ivan.briano@intel.com>
After activation of cube based driver support on L4 and F3 series,
this commits performs the clean up of F3 and L4 relative code to
native clock control drivers.
Indirectly, it makes pwm driver supported de facto on F3 series
Change-Id: Idac17103a9b5ef6eab540719343cc8f5865f15fa
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
After introducing STM32Cube based clock control driver for
stm32 family, update GPIO driver to support it.
Once supported across the whole family, we clean up will be done.
Change-Id: If50cb580cb01dc1d38557e54f19a8260feaa504e
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
This commit removes unnecessary CONFIG_SYS_POWER_DEEP_SLEEP protection
in shim drivers as QMSI 1.4 has introduced empty context save/restore
functions that can be called in Quark D2000, therefore keeping common
code at the shim driver level for Quark SE and D2000.
Change-Id: Ia2a466327f999668c6511c0193014e9151bff6ae
Signed-off-by: Juan Solano <juanx.solano.menacho@intel.com>
Several GPIO device drivers support only one of the two possible
access_op modes and return an errno error code for the mode they do
not support. Use the same errno code across all drivers.
Change-Id: Ic01ce9dee7fb2405d254c60cebee22053c803270
Signed-off-by: Marcus Shawcroft <marcus.shawcroft@arm.com>
Several GPIO drivers detect an out of range pin number and return an
errno error code. Use the same errno code across all drivers.
Change-Id: I0e2949432d6845d12c37064c78f9c228b8e8e45a
Signed-off-by: Marcus Shawcroft <marcus.shawcroft@arm.com>
Several gpio drivers consider GPIO_INT with GPIO_DIR_OUT to be illegal
and return an errno code. Use the same errno code across all drivers.
Change-Id: I1594df0cfdf96194685c83c34dff36261896f2de
Signed-off-by: Marcus Shawcroft <marcus.shawcroft@arm.com>
Implement the missing port read and write behaviour.
Change-Id: I0928379eddf81d806a0ae6b75a1ea2993c3a28ff
Signed-off-by: Marcus Shawcroft <marcus.shawcroft@arm.com>
Adjust the implementation of gpio_pin_read() to return 0 or 1 rather
than 0 or 2^pin. This ensures consistent behaviour with other gpio
device drivers, and conforms to the behaviour documented in gpio.h by
the previous patch.
Change-Id: Ia02aa68105a406f355d16a3f9b0550f948658483
Signed-off-by: Marcus Shawcroft <marcus.shawcroft@arm.com>
Extended the nRF5 GPIO driver to support configurable pin drive
strengths.
Change-Id: I59c42b8a69cc37b594c2388b892d3accd7b19807
Signed-off-by: Marcus Shawcroft <marcus.shawcroft@arm.com>
The NXP copyright should not have 'Semiconductors, Inc' in it.
Change-Id: I6e290146d49bf22d1d40b7fa764bb53b6b122303
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
The commit c90e4d063be0ff5f47df45ca8500eff8518c5d25 changed
line 216 in drivers/gpio/gpio_stm32.c:
-elif CONFIG_SOC_SERIES_STM32F4X
+#elif /* CONFIG_SOC_SERIES_STM32F4X */
This causes the following compiler error:
zephyr/drivers/gpio/gpio_stm32.c:218:39: error: #elif with no expression
#elif /* CONFIG_SOC_SERIES_STM32F4X */
^
Change-Id: Ie8b124931e333aa7860e6db22f5c259670e29833
Signed-off-by: Michael Scott <michael.scott@linaro.org>
Implementation includes adding some defines in the pinmux,
adjusting gpio driver to specific defines for STM32F3X family,
adding specific functionality in the F3X SoC definition.
Change-Id: I465c66eb93e7afb43166c4585c852e284b0d6e67
Signed-off-by: Adam Podogrocki <adam.podogrocki@rndity.com>
This is one of the series of patches that simplifies the driver
code by using the IS_ENABLED macro. This removes the need of the
const variable and the three wrapper functions on semaphore APIs.
Jira: ZEP-1251
Change-Id: I5102e8674663ddbfc65220de72c8b778a9ec726c
Signed-off-by: Kuo-Lang Tseng <kuo-lang.tseng@intel.com>
Replace the existing Apache 2.0 boilerplate header with an SPDX tag
throughout the zephyr code tree. This patch was generated via a
script run over the master branch.
Also updated doc/porting/application.rst that had a dependency on
line numbers in a literal include.
Manually updated subsys/logging/sys_log.c that had a malformed
header in the original file. Also cleanup several cases that already
had a SPDX tag and we either got a duplicate or missed updating.
Jira: ZEP-1457
Change-Id: I6131a1d4ee0e58f5b938300c2d2fc77d2e69572c
Signed-off-by: David B. Kinder <david.b.kinder@intel.com>
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
tested with blinky, button and disco apps
Change-Id: I4b520d4f3e42c97e4a723747ce4a6c67ca9f1d18
Signed-off-by: Jean-Paul Etienne <fractalclone@gmail.com>
Now that we have a more generic mcux gpio driver that can be used across
multiple Kinetis SoCs, remove the specific k64 gpio driver.
Jira: ZEP-1394
Change-Id: I177f96a75e441b70c523e74e99f1b7a54eac6b0e
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
Adds a new mcux gpio driver that can be used for k64 and other Kinetis
SoCs. This driver uses mcux CMSIS register accesses to the GPIO and PORT
modules. Some of the logic from the k64 gpio driver was reused and
refactored (mainly flag parsing and callback handling).
Jira: ZEP-1394
Change-Id: If5e9390861c181ec555dce6569b14debb729526a
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
Remove legacy option and use SYS_CLOCK_EXISTS where appropriate.
Change-Id: I3d524ea2776e638683f0196c0cc342359d5d810f
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
drivers/gpio/gpio_pcal9535a.c defines a nano_timer,
but never uses it. So delete it.
gpio_sch.c uses a k_timer, but gpio_sch.h defines a
nano_timer. So change the variable poll_timer to
type k_timer.
Jira: ZEP-1525
Change-Id: I884e4703c1ace61da5be7d9c63e58e7c3bce7f68
Signed-off-by: Qiu Peiyang <peiyangx.qiu@intel.com>
replace include <nanokernel.h> with <kernel.h> everywhere and also fix
any remaining mentions of nanokernel.
Keep the legacy samples/tests as is.
Change-Id: Iac48447bd191e83f21a719c69dc26233216d08dc
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
The GPIO_INT_LEVEL value is zero so the mask assignement
is never executed. Using the bit complement GPIO_INT_EDGE
the proper mask is assigned
This issue was reported by Coverity
Coverity-CID: 151966
Change-Id: Iacfeb6466388023bd6123ba86280aa9ca15f34e4
Signed-off-by: Sergio Rodriguez <sergio.sf.rodriguez@intel.com>
The GPIO_INT_LEVEL and GPIO_INT_ACTIVE_LOW values are zero so the
statements are never executed then is better use the bit complement
masks
This issue was reported by Coverity
Coverity-CID: 157586
Change-Id: Ic8b20660a991dd3d0c71248f84c917e5ce5c3c7c
Signed-off-by: Sergio Rodriguez <sergio.sf.rodriguez@intel.com>
To support interrupt-based GPIO callbacks in the nRF5x series one needs
to use the GPIOTE module, which has a series of channels that can be
programmed to trigger interrupts on level changes.
This commit adds basic support for the GPIOTE module within the nRF5x
GPIO driver, as well as callback support in order for basic buttons and
switches to work.
Change-Id: I9ae600f894372ad42b09a18cc38a90fc29abb0df
Signed-off-by: Carles Cufi <carles.cufi@nordicsemi.no>
The pinmux configuration is done during board initialization.
This was validated using the following Zephyr apps:
- samples/basic/blinky
- samples/basic/disco
- samples/basic/button
All 4 GPIO ports are supported.
Change-Id: If8599a23c1d56cfd678a6e2e5339f7e093c6061a
Signed-off-by: Gil Pitney <gil.pitney@linaro.org>
Move logging out of misc/ to its own subsystem. Anything related to
logging and any new logging features or backends could be added here
instead of the generic location in misc/ which is overcrowded with
options that are not related to eachother.
Jira: ZEP-1467
Change-Id: If6a3ea625c3a3562a7a61a0ba5fd7e6ca75518ba
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
This patch enables the clock control interface into the ARM LTD
Beetle GPIO driver.
Jira: ZEP-1300
Change-Id: I576767b68a8e4aa965d34716528df3bb4e837d73
Signed-off-by: Vincenzo Frascino <vincenzo.frascino@linaro.org>
Add the support for all the GPIO port of the L4.
Change-Id: Id365e17223cd5c49443df9fb6b96a3c4f204f523
Signed-off-by: Fabien Parent <fparent@baylibre.com>
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
This commit replaces the nanokernel.h include by kernel.h.
Change-Id: Ib42fbf2d9f77a73c0831f569b3dbbfb342ea2e1d
Signed-off-by: Flavio Santes <flavio.santes@intel.com>
This fixes an always false evaluation of the gpio I/O direction
This issue was reported by Coverity
Coverity-CID: 151978
Change-Id: I93ec3319a3f18d564c961a5cbd9dcc9c60efbeb7
Signed-off-by: Sergio Rodriguez <sergio.sf.rodriguez@intel.com>
The GPIO_INT_ACTIVE_LOW value is zero so the mask assignement is
never executed. Using the bit complement GPIO_INT_ACTIVE_HIGH the
proper mask is assigned
This issue was reported by Coverity
Coverity-CID: 151966
Change-Id: Ibc7d2e4c3ebee249b5ab9719f8177cc14c0d1d33
Signed-off-by: Sergio Rodriguez <sergio.sf.rodriguez@intel.com>
This fixes an always false evaluation of the gpio I/O direction
This issue was reported by Coverity (CID 150821).
Change-Id: I6c0e9fe405cbd3e35454a81754fa0b1c721691f0
Signed-off-by: Sergio Rodriguez <sergio.sf.rodriguez@intel.com>
This fixes an always false evaluation of the gpio I/O direction
This issue was reported by Coverity
Coverity-CID: 151833
Change-Id: Ie952d6f50c0383d5631325b69e8e8b234c67c4b8
Signed-off-by: Sergio Rodriguez <sergio.sf.rodriguez@intel.com>
This fixes an always false evaluation of the gpio I/O direction
This issue was reported by Coverity
Coverity-CID: 151834
Change-Id: I033e368b2e91d888f2e8a797490df757513c3906
Signed-off-by: Sergio Rodriguez <sergio.sf.rodriguez@intel.com>
This patch addresses the following issues:
* Aligns the Kconfig code style with Zephyr projects requirements.
* Removes redundant "depends on" from Kconfig.
* Adds static to the gpio_dw_isr declaration.
* Adds guards to the header files.
Change-Id: I1ae70868f0bda97891cbeb494e5efba1bd537aa1
Signed-off-by: Vincenzo Frascino <vincenzo.frascino@linaro.org>
This patch addresses the following issues:
* Aligns the Kconfig code style with Zephyr projects requirements.
* Removes redundant "depends on" from Kconfig.
Change-Id: I4c8df0999f92a834d4023ce5856a2a6c39797c00
Signed-off-by: Vincenzo Frascino <vincenzo.frascino@linaro.org>
This patch removes a redundant "depends on" from the gpio Kconfig for
nRF5X family.
Change-Id: I28ac15b58839e05f47ade81bef66a03a0a44bebd
Signed-off-by: Vincenzo Frascino <vincenzo.frascino@linaro.org>
This patch addresses the following issues:
* Aligns the Kconfig code style with Zephyr projects requirements.
* Removes redundant "depends on" from Kconfig.
* Adds static to the gpio_sam3_init declaration.
Change-Id: If5c8a1822d6c116ea34d0f220f3e5fa359b6fa18
Signed-off-by: Vincenzo Frascino <vincenzo.frascino@linaro.org>
Use unified kernel APIs and align syntax after function name changes.
Change-Id: I028f4faeaf33e28197d5f705063459188272027d
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
This commit updates the gpio_qmsi_ss driver by adding save/restore
context functionality for power management, using the corresponsing
QMSI APIs.
Jira: ZEP-665
Change-Id: I5d8b6050f5b099678b7e6d9144907ea2ce2dda4b
Signed-off-by: JuanX Solano Menacho <juanx.solano.menacho@intel.com>
The driver is currently used only by the ARM Beetle platform.
Jira: ZEP-1245
Change-Id: I6611edd7486a3c6d82d66a9a96c5d4860dad1539
Signed-off-by: Vincenzo Frascino <vincenzo.frascino@linaro.org>
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
PRIMARY, SECONDARY, NANOKERNEL, MICROKERNEL init levels are now
deprecated.
New init levels introduced: PRE_KERNEL_1, PRE_KERNEL_2, POST_KERNEL
to replace them.
Most existing code has instances of PRIMARY replaced with PRE_KERNEL_1,
SECONDARY with POST_KERNEL as SECONDARY has had a longstanding bug
where the documentation specified SECONDARY ran before the kernel started
up, but actually ran afterwards.
Change-Id: I771bc634e9caf7f17dbf214a270bc9967eed7d32
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
It's unused anywhere and unlikely to be in the future.
Change-Id: I57926e91da7d31ef6ddda4f86e6dac103dbfa176
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
This commit updates the gpio_qmsi driver by removing the temporary
Zephyr save/restore context implementation and using the new QMSI APIs.
Jira: ZEP-999
Change-Id: Ic7b80a8f86baa7a6be11c93bbdebb18a102b0221
Signed-off-by: JuanX Solano Menacho <juanx.solano.menacho@intel.com>
For AON peripherals on Quark SE C1000, an API is needed
to retrieve the interrupt status after wake up.
This enables the application to know the wake source before
enabling again the interrupts.
Add this API to the gpio as this is a wake event
on Quark SE C1000.
Jira: ZEP-1188
Change-Id: Icc4aa6617bf18402b7e5dc3aab779ec2964e1c5b
Signed-off-by: Julien Delayen <julien.delayen@intel.com>
The GPIO and AON GPIO ports are available to both the x86 and ARC
cores, but the driver always assumed only the x86 at the time of
configuring interrupts.
Use the available macros to set the correct values independently of
which core it's being built for.
Jira: ZEP-1030
Change-Id: I310afcc48780fbe1cac9dc3368a6de11bd797fda
Signed-off-by: Iván Briano <ivan.briano@intel.com>
The SoC level peripherals are accesible by both cores, while the SS
ones are only available to the sensor subsystem. Since the ARC core can
make use of both drivers at the same time, we need to be able to
differentiate their configuration values somehow.
Also disable the SoC GPIO for the ARC by default, as it still needs
more changes to be usable.
Jira: ZEP-1030
Change-Id: Ic5415c404ecd32a3e560467b6f5eaa873a515d72
Signed-off-by: Iván Briano <ivan.briano@intel.com>
The callback from the QMSI driver now can take a data pointer to pass
to the given function, so use that to pass the device to our callback
instead of defining one function for each supported port.
Change-Id: I82d863314e0443b7c4a12d4a9ad763b9634ca8e2
Signed-off-by: Iván Briano <ivan.briano@intel.com>
Update the QMSI drop we maintain in Zephyr, and fix the build where
needed:
- QM_SCSS_INT is renamed to QM_INTERRUPT_ROUTER;
- every member of QM_INTERRUPT_ROUTER was renamed as well;
- QM_IRQ_* renamed too, mostly added _INT at the end;
- some isr functions were renamed to keep their names consistent;
- build for x86 needs to define QM_LAKEMONT, as QM_SENSOR was for ARC.
Change-Id: I459029ca0d373f6c831e2bb8ebd52402a55994d1
Signed-off-by: Iván Briano <ivan.briano@intel.com>
Implements MCU-specific GPIO input interrupt integration. Added
definition of System configuration controller as well as its needed by
the GPIO code.
The SYSCFG controller is used for system-specific configuration such as:
- remap the type of memory accessible at address 0x00000000
- manage the external interrupt line connection to GPIOs
- configure the I/O compensation cell
Change-Id: Id2ebfbd1b21e77be76406d1cd6cd5d4989e9e2fa
Signed-off-by: Ricardo Salveti <ricardo.salveti@linaro.org>
Signed-off-by: Amit Kucheria <amit.kucheria@linaro.org>
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
STM32F4 requires the alternative function config to be set, so just
initialize that as part of the gpio configure call.
Change-Id: I33a4a8efec59c5ebe7dc3f3580f0dd2bf7ded7f4
Signed-off-by: Ricardo Salveti <ricardo.salveti@linaro.org>
Signed-off-by: Amit Kucheria <amit.kucheria@linaro.org>
Make default value compatible with both nRF51 and nRF52.
Change-Id: I65dafbdf8518103becdd7388e9c0195ef1c4460d
Signed-off-by: Ricardo Salveti <ricardo.salveti@linaro.org>
PCI enumeration modifies pci_dev and base_addr at driver
initialization therefore these objects move from config_info to
driver_data in preparation for config_info becoming const.
We drop code that attempts to update irq_num based on PCI enumeration
because the interrupt found by PCI enumeration must always be the same
as the statically configured IRQ number.
Change-Id: Ibfefa851d2836d524b8151ed0108ecf9de2cd3a3
Signed-off-by: Marcus Shawcroft <marcus.shawcroft@arm.com>
Since dd5e90ec the device_get_binding call returns NULL unless the
driver_api is set by the driver. Since the exti driver only uses an
internal struct to store the callbacks, remove the need for the device
binding call from other drivers (e.g. gpio).
Change-Id: If0b733c27754108118d87ef02640311f0535ab57
Signed-off-by: Ricardo Salveti <ricardo.salveti@linaro.org>
Signed-off-by: Amit Kucheria <amit.kucheria@linaro.org>
The k64 pinmux driver can be used for any k64 board, not just frdm_k64f,
therefore renaming the driver accordingly.
Change-Id: I45e96d4a5ff6aa859d0f57fe098e44a8ae5283d1
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
The callback list within the driver config is updated dynamically
hence the list itself cannot be const. Create a runtime context
driver data structure and relocate the callback list to the new
structure.
Change-Id: Ied20846e6a78e43967239afa7797456a9abd8548
Signed-off-by: Marcus Shawcroft <marcus.shawcroft@arm.com>
Using AON for GPIO kconfigs is very specifc to quark se, there
is no need to make this special for this platform. Use the
existing scheme instead.
Change-Id: I946431490380dc0f537d6056277a94c9c9c80fed
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
