Unified kernel does not provide the _thread_arg_t type, but instead uses
void * directly for its thread entry parameters. _thread_entry_t is
typedefed from void * anyway, and only obfuscates the type. So, define
_thread_entry_t to be a function pointer to a function with three void *
parameters, and when the unified kernel becomes the only kernel, all the
_thread_arg_t types will go away.
With this change, IAMCU runs all the tests sysV x86 is able to run as a
unified kernel.
Change-Id: I53c8754629a5a0a114a16a775ff1efc1884496ff
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
The x86 architecture port is fitted with support for the unified kernel,
namely:
- the interrupt exit code now calls _Swap() if the current
thread is not a coop thread and if the scheduler is not locked
- there is no 'task' fields in the _nanokernel anymore: _Swap()
now calls _get_next_ready_thread instead
- the _nanokernel.fiber field is replaced by a more sophisticated
ready_q, based on the microkernel's priority-bitmap-based one
- nano_private includes nano_internal.h from the unified directory
- the FIBER, TASK and PREEMPTIBLE flags do not exist anymore: the thread
priority drives the behaviour
- the tcs uses a dlist for queuing in both ready and wait queues instead
of a custom singly-linked list
- other new fields in the tcs include a schedule-lock count, a
back-pointer to init data (when the task is static) and a pointer to
swap data, needed when a thread pending on _Swap() must be passed more
then just one value (e.g. k_stack_pop() needs an error code and data)
- fiberRtnValueSet() is aliased to _set_thread_return_value since it
also operates on preempt threads now
- _set_thread_return_value_with_data() sets the swap_data field in
addition to a return value from _Swap()
- convenience aliases are created for shorter names:
- _current is defined as _nanokernel.current
- _ready_q is defined as _nanokernel.ready_q
- _Swap() sets the threads's return code to -EAGAIN before swapping out
to prevent timeouts to have to set it (solves hard issues in some
kernel objects).
- Floating point support.
Note that, in _Swap(), the register holding the thread to be swapped in has
been changed from %ecx to %eax in both the legacy kernel and the unified kernel
to take advantage of the fact that the return value of _get_next_ready_thread()
is stored in %eax, and this avoids moving it to %ecx.
Work by: Dmitriy Korovkin <dmitriy.korovkin@windriver.com>
Allan Stephens <allan.stephens@windriver.com>
Benjamin Walsh <benjamin.walsh@windriver.com>
Change-Id: I4ce2bd47bcdc62034c669b5e889fc0f29480c43b
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
Loading the _nanokernel address in %edi rather than in %eax allows
calling funtions in _Swap() without having to restore it, since %eax is
used for the return value. %edi is a callee-saved register and does not
have to be restored.
Change-Id: I338086d8e15857e835d5d7487de975791926f869
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
Quark D2000 and SE based boards (but Arduino 101) use QMSI bootloader
by default. QMSI bootloader sets up GDT in the so-called 'basic flat
model' just like Zephyr does by default.
This patch changes Quark D2000 and SE boards default configuration
so they rely on QMSI bootloader and we don't sets up GDT twice.
Change-Id: Ic6e520148b732bd48c00657c6c8138a8d865faef
Signed-off-by: Andre Guedes <andre.guedes@intel.com>
_irq_controller_isr_vector_get() now returns -1 if it couldn't
determine which vector was activated.
Issue: ZEP-602
Change-Id: Ib0f5dbc3b68cc5e2c3a23121530e178aede20d06
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Change the signal ramp up/down config parameters in i2c driver
module to SoC specific.
Jira: ZEP-753
Change-Id: Ie01f1d890a7133d30ea53eee07f60354734a8571
Signed-off-by: Baohong Liu <baohong.liu@intel.com>
Originally, x86 just supported APIC. Then later support
for the Mint Valley Interrupt Controller was added. This
controller is mostly similar to the APIC with some differences,
but was integrated in a somewhat hacked-up fashion.
Now we define irq_controller.h, which is a layer of abstraction
between the core arch code and the interrupt controller
implementation.
Contents of the API:
- Controllers with a fixed irq-to-vector mapping define
_IRQ_CONTROLLER_VECTOR_MAPPING(irq) to obtain a compile-time
map between the two.
- _irq_controller_program() notifies the interrupt controller
what vector will be used for a particular IRQ along with triggering
flags
- _irq_controller_isr_vector_get() reports the vector number of
the IRQ currently being serviced
- In assembly language domain, _irq_controller_eoi implements
EOI handling.
- Since triggering options can vary, some common defines for
triggering IRQ_TRIGGER_EDGE, IRQ_TRIGGER_LEVEL, IRQ_POLARITY_HIGH,
IRQ_POLARITY_LOW introduced.
Specific changes made:
- New Kconfig X86_FIXED_IRQ_MAPPING for those interrupt controllers
that have a fixed relationship between IRQ lines and IDT vectors.
- MVIC driver rewritten per the HAS instead of the tortuous methods
used to get it to behave like LOAPIC. We are no longer writing values
to reserved registers. Additional assertions added.
- Some cleanup in the loapic_timer driver to make the MVIC differences
clearer.
- Unused APIs removed, or folded into calling code when used just once.
- MVIC doesn't bother to write a -1 to the intList priority field since
it gets ignored anyway
Issue: ZEP-48
Change-Id: I071a477ea68c36e00c3d0653ce74b3583454154d
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
The toolchain headers included an abstraction for defining symbol
names in assembly context in the situation where we're using a
DOS-style assembler that automatically prepends an underscore to
symbol names.
We aren't. Zephyr is an ELF platform. None of our toolchains do
this. Nothing sets the "TOOL_PREPENDS_UNDERSCORE" macro from within
the project, and it surely isn't an industry standard. Yank it out.
Now we can write assembler labels in natural syntax, and a few other
things fall out to simplify too.
(NOTE: these headers contain assembly code and will fail checkpatch.
That is an expected false positive.)
Change-Id: Ic89e74422b52fe50b3b7306a0347d7a560259581
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
Completing the terminology change started with change 4008
by updating the Kconfig files processed to produce the
online documentation, plus header files processed by
doxygen. References to 'platform' are change to 'board'
Change-Id: Id0ed3dc1439a0ea0a4bd19d4904889cf79bec33e
Jira: ZEP-534
Signed-off-by: David B. Kinder <david.b.kinder@intel.com>
A previous re-work of IRQ priorities was led astray by an incorrect
comment. Priority level 1 is not a non-maskable interrupt priority.
In addition, zero latency IRQs are not implemented on ARC.
Timer driver now doesn't specify IRQ_ZERO_LATENCY (as that wouldn't be
correct) and its IRQ priority is now tunable in Kconfig. The default is 0.
IPM driver on both ARC and x86 side were being configured with hard-coded
priority of 2, which wasn't valid for ARC and caused an assertion failure.
The priority level is now tunable with Kconfig and defaults to 1 for ARC.
Issue: ZEP-693
Change-Id: If76dbfee214be7630d787be0bce4549a1ecbcb5b
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
QMSI boot loader uses GPS0. power.c should use GPS1 for its
purpose because GPS1 is reserved for PM use. Switched to
use GPS1 instead.
Jira: ZEP-647
Change-Id: I653450cd0b42aa80bef21c8a42f4aa39cdaef2ed
Signed-off-by: Ramesh Thomas <ramesh.thomas@intel.com>
The boot initialization and boot process of the sensor sub systems
is now using the new system log macros and updated the Kconfig
variable to be a level rather than a bool.
Change-Id: I098143684f8e7077a525e7fcbc93b42b22d427ac
Signed-off-by: Genaro Saucedo Tejada <genaro.saucedo.tejada@intel.com>
Previously, exception stubs had to be declared in assembly
language files. Now we have two new APIs to regsiter exception
handlers at C toplevel:
_EXCEPTION_CONNECT_CODE(handler, vector)
_EXCEPTION_CONNECT_NOCODE(handler, vector)
For x86 exceptions that do and do not push error codes onto
the stack respectively.
In addition, it's now no longer necessary to #define around
exception registration. We now use .gnu.linkonce magic such that
the first _EXCEPTION_CONNECT_*() that the linker finds is used
for the specified vector. Applications are free to install their
own exception handlers which will take precedence over default
handlers such as installed by arch/x86/core/fatal.c
Some Makefiles have been adjusted so that the default exception
handlers in arch/x86/core/fatal.c are linked last. The code has
been tested that the right order of precedence is taken for
exceptions overridden in the floating point, gdb debug, or
application code. The asm SYS_NANO_CPU_EXC_CONNECT API has been
removed; it was ill- conceived as it only worked for exceptions
that didn't push error codes. All the asm NANO_CPU_EXC_CONNECT_*
APIs are gone as well in favor of the new _EXCEPTION_CONNNECT_*()
APIs.
CONFIG_EXCEPTION_DEBUG no longer needs to be disabled for test
cases that define their own exception handlers.
Issue: ZEP-203
Change-Id: I782e0143fba832d18cdf4daaa7e47820595fe041
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Created set of functions that was designed in the original RFC to
contain arch and soc specific code. This makes the interface to
the OS PM infrastructure cleaner and makes it easier to understand
the flow in the sample app. Also it makes code reuse easier across
soc/arch implementations. These are open to change in future if
other means to achieve the same goals are in place.
Jira: ZEP-227 ZEP-225
Change-Id: Ief57871c370341c55009ad4f456b7f71f2c2a3c6
Signed-off-by: Ramesh Thomas <ramesh.thomas@intel.com>
The interrupt stack wasn't being initialized at boot.
Change-Id: Iec3e770d385643415641e15906c3a53f7c74a2e9
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Until now, EOI had always been sent out to the APIC with interrupts
unlocked. Depending on timing, there is a race where the next interrupt
on the same line could arrive before _IntExit disables interrupts
and pops context. If this happens consecutively enough times, the
interrupt stack will overflow.
Now we disable interrupts at the beginning of _IntExitWithEoi and they
remain that way until 'iret'.
Change-Id: Ibb28e0db902ff483d7a885389f231ac2d1864657
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Arches now select whether they want to use the GCC built-ins,
their own assembly implementation, or the generic C code.
At the moment, the SDK compilers only support builtins for ARM
and X86. ZEP-557 opened to investigate further.
Change-Id: I53e411b4967d87f737338379bd482bd653f19422
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
When CONFIG_SYS_POWER_DEEP_SLEEP is enabled, the _sys_soc_resume
function is called and the 'ZF' bit from EFLAGS register may be set
to 1. In that case, we end up wrongly jumping into 'copyDataDone'
label and no data is copied from ROM to RAM.
It seems this 'je' instruction is used without any previous comparison
operation which properly sets the ZF flag. Since 'ZF' initial value is
0, we never jump into 'copyDataDone' label. Also, this 'je' instruction
doesn't seem to be really required since, if %ecx is zero, no data will
be copied anyway.
That being said, this patch removes the 'je' instruction since it fixes
the bug described in the first paragraph and it doesn't affect the rest
of the crt0 execution.
Also, removes outdated information about section size and alignment.
Change-Id: Ia062b78247c4059009193a53f879aa1ebe80881d
Signed-off-by: Andre Guedes <andre.guedes@intel.com>
Signed-off-by: Iván Briano <ivan.briano@intel.com>
This patch basically reverts patch "QMSI/uart: Use IOAPIC_EDGE instead
of IOAPIC_LEVEL". The issue with lost UART interrupts is fixed with
following patch: "_loapic_isr_vector_get: fix implementation" which is
a proper way.
Change-Id: I07aa168335827b09db7fcb2486b01585648ff5d6
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Some issues have been noted with nested interrupts on quark SE.
In particular, the wrong vector # being sent to the IOAPIC EOI
register. Now when doing EOI, we lock interrupts so that the act
of reading the current vector being serviced, and sending EOI
to both controllers happens atomically.
Change-Id: Id9ad992740e197bb9d4638764952b04a27c4af61
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
The '_sys_soc_resume' symbol is function-type not data-type as declared
in crt0.S. This patch fixes this by using GTEXT macro instead.
Change-Id: Ibe8bcf92ab045bfe908fd2048d046083e773894f
Signed-off-by: Andre Guedes <andre.guedes@intel.com>
Having two parallel implementations is a maintenance issue, especially
when some strategically placed #ifdefs will suffice.
We prefer the ASM versions for SYS V, as we need complete control of
the emitted assembly for interrupt handling and context switching.
The SYS V code is far more mature. IAMCU C code has known issues with
-fomit-frame-pointer.
The only difference between the two calling conventions is that the
first three function arguments are provided in eax, edx, ecx instead
of on the stack.
Issue: ZEP-49
Change-Id: I9245e4b0ffbeb6d890a4f08bc8a3a49faa6d8e7b
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Since we started to use UART_IRQ_FLAGS define them also for
quark_d2000 board. Note that we use IOAPIC_LEVEL since this is right
thing to do and the issue with lost interrupts is fixed in
_loapic_isr_vector_get().
Change-Id: Iaed0283bcc01290e420b42ff5d40ce9d99bfc677
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Use IOAPIC_EDGE instead of IOAPIC_LEVEL to fix missing interrupts.
During tests it was found that using IOAPIC_LEVEL interrupts for UART at
some points are lost.
Proposed by Calando, Antoine <antoine.calando@intel.com>
Change-Id: I18b20217c4d73fdeaa424bf59d00f6be1ec6ef1b
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
We no longer assume pointer sizes are the same between host and
target, and use stdint defintions to size things.
Change-Id: Ie4dc41c60d62931fdb3d1764ade01c16a64d0b54
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Quark SE USB device (Designware IP) controller driver implements
the low level control routines to deal directly with the hardware.
Only FIFO mode supported.
Change-Id: I086186df017734579f0363ed79effc1481ff32c2
Signed-off-by: Adrian Bradianu <adrian.bradianu@windriver.com>
Signed-off-by: Jesus Sanchez-Palencia <jesus.sanchez-palencia@intel.com>
Signed-off-by: Jithu Joseph <jithu.joseph@intel.com>
Change the LOAPIC timer IRQ number to 10. It should not
be 0.
Change-Id: I156286d0e3b903cca07cc3f87804b145aacaf117
Signed-off-by: Baohong Liu <baohong.liu@intel.com>
No code uses it and it being undefined anywhere generates a
documentation warning.
Change-Id: I09de2e58edf82e7fb9780a5dea98a282502436b6
Signed-off-by: Inaky Perez-Gonzalez <inaky.perez-gonzalez@intel.com>
Introduce a soc-cflags, soc-cxxflags, and soc-aflags as a means for
SoC specific compiler flags to be set without manipulating Kbuild
options directly.
Change-Id: I2c8f5019fb237429e59717ef96bd4251a61dc1a5
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
For some security scenarios the GDT may already be setup and locked,
in which case the kernel trying to set it again could lead to problems.
Change-Id: I727c1d213479f46a4bb6f0c04a9096131e10b3e7
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Convert leading whitespace into tabs in Kconfig files. Also replaced
double spaces between config and <prompt>.
Change-Id: I341c718ecf4143529b477c239bbde88e18f37062
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Add missing Kconfig files and connections to expose Kconfig options
in ext/ directories. Fixup QMSI to only be exposed on platforms that
utilize it.
Change-Id: I6c6c5011b2bf2966f65aa8279dc594a244821956
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Fixes a bug in _ExcEntSetupDone wherein the return address to the
exception stub was accidentally changed to point to the TCS of the
interrupted thread.
Jira: ZEP-378
Change-Id: I0e502649c49c35ba8b2457016ede4a6b586da3fb
Signed-off-by: Peter Mitsis <peter.mitsis@windriver.com>
We had wrong logic and confusing config options for debugging
Quark SE sensor subsystem. The new option will be used for GDB
debugging. The existing DEBUG option will be used for printing
additional messages on the screen while booting the sensor
sub-system.
Change-Id: Ia54d22e872edafe531ccde271e7504fe9c48a73a
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Use the same Kconfig infrastructure and options for all SPI drivers.
Jira: ZEP-294
Change-Id: I7097bf3d2e1040fcec166761a9342bff707de4dd
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Most of the values are SoC specific and come from the SoC definition,
not need to define them in Kconfig.
Jira: ZEP-294
Change-Id: I7688ca523915e3fa8a1d28dea7a1d84a66b39d56
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Avoids confusion with .gitignore rules, which were inadequate to
cover all the places where these files are found. At least in
VIM, these files are now syntax highlighted correctly.
Change-Id: I23810b0ed34129320cc2760e19ed1a610afe039e
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Fibers initialize this back pointer to NULL as they are (by definition)
not microkernel tasks. Microkernel tasks initialize it to their
corresponding 'ktask_t'.
However for nanokernel systems, the back pointer is always NULL. This
is because there is only one task in a nanokernel system (the background
task) and it can not pend on a nanokernel object--it must poll.
Change-Id: I9840fecc44224bef63d09d587d703720cf33ad57
Signed-off-by: Peter Mitsis <peter.mitsis@windriver.com>
Adds a back pointer to the microkernel task to the TCS when
configured for a microkernel. This is a necessary prerequisite
to support microkernel tasks pending on nanokernel objects.
Change-Id: Ia62f9cf482ca20b008772dad80cbfd6acb6f5b7a
Signed-off-by: Peter Mitsis <peter.mitsis@windriver.com>
We really should have more faith in the compiler, it generates
code to implement this exactly like the arch-specific assembly
versions, and on ARM is actually 4 bytes shorter.
FUNC_NO_FP used to disable the usual C preamble to update the
frame/stack pointers, which is how the sizes are still the same
or less. It's debatable how useful the occasional use of
FUNC_NO_FP is in practice since it hinders debugging and in a
production build frame pointers should be globally disabled, but
we can address that later.
Change-Id: I6c4b64ab3e3a9b6f91d52fa8c92e6e79a986fc77
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Of the 3 related functions;
_thread_essential_set()
_thread_essential_clear()
_is_thread_essential()
The first two are parameter-less and always operate on
"_nanokernel.current". The last one takes a 'thread' parameter but will
operate on _nanokernel.current if the parameter is NULL. All calls to
_is_thread_essential() pass NULL!
This change makes the 3 functions consistent by removing the parameter
to the 3rd function. This should also be marginally more efficient,
though consistency was the motivation. This change corrects the doc
preamble to all 3 functions.
(These functions would probably be better as inlines. Also, the choice
of when to use wrappers seems a bit arbitrary. E.g. there's nothing
for setting/testing the "FIBER" flag.)
Change-Id: Ie3589f8a28b227c6d7a3a31b664d3b3e6e9c6d17
Signed-off-by: Geoff Thorpe <geoff.thorpe@nxp.com>
Other IOs use this format, so lets be consistent and use
I2C_0 instead of I2C0 and I2C_1 an instead of I2C1.
Change-Id: I591ab08e14bd533ef0fac38e596559da783863b8
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Instead of defining the output format in the toolchain environment
setup, define this per SoC that supports the ABI.
This will allow us to directly referencing an installed toolchain
without the need for declaring ZEPHYR_GCC_VARIANT
Change-Id: Icd1a7a21acbf075a51854fb2ebb3ef06788ce9b5
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
For Quark D2000 we use QMSI drivers, so the initialisation code is no
longer needed.
Change-Id: I22aaa35288e230c455a19b9e67dc6cfb7dc0ff12
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
QMSI defines all the registers of the SoC and other values in
qm_soc_regs.h, so cleanup soc.h and rely on the data from the BSP
contained in qm_soc_regs.h.
Change-Id: I672925cf1c0144a9ed64073ea289c691285a8082
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Fix naming and use a global driver name for instance.
Change-Id: I30a54cb9c20773e1b6fdc57b934aa564612a6c45
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
With most boards there's no simple way to get access to the HCI
traffic. Simultaneously these boards only have one external UART for
the console. This patch introduces a protocol which combines both
normal logs and HCI logs over a single binary protocol sent over the
console UART.
The protocol is modeled based on the btsnoop/monitor protocols used by
BlueZ, and the first tool that's able to decode this is btmon from
BlueZ ("btmon --tty <tty>").
For platforms with two or more external UARTs it is still possible to
use CONFIG_UART_CONSOLE as long as the UART devices used are
different, however on platforms with a single external UART
UART_CONSOLE should be disabled if BLUETOOTH_DEBUG_MONITOR is enabled
(in this case printk/printf get encoded to the monitor protocol).
Origin: Original
Change-Id: I9d3997c7a06fe48e7decb212b2ac9bd8b8f9b74c
Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
Use SOC_FAMILY and SOC_SERIES to identify soc families and series
and to point to the correct linker files and files related to a
specific SoC.
Change-Id: I8b1a7339f37d6ea4161d03073d36557a40c0b4a6
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
GDB server needs ownership of some exceptions to display information when
taking a fatal exception (DIVIDE_ERROR, PAGE_FAULT).
Introduce a Kconfig option that can work for any debugger.
Change-Id: I39aef22a820543a7fe9ac333b487592946abc0f3
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
The GDB server implements a set of GDB commands, such as read/write
memory, read/write registers, connect/detach, breakpoints, single-step,
continue. It is not OS-aware, and thus provides a 'system-level'
debugging environment, where the system stops when debugging (such as
handling a breakpoint or single-stepping).
It currently only works over a serial line, taking over the
uart_console. If target code prints over the console, the GDB server
intecepts them and does not send the characters directly over the serial
line, but rather wraps them in a packet handled by the GDB client.
Change-Id: Ic4b82e81b5a575831c01af7b476767234fbf74f7
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
Introduce an x86 interrupt stack frame that contains more information
than the non-debug one, namely the caller-saved GPRs, as well as an API
to retrieve it. Able to handle nested interrupts stack frames.
Change-Id: If182aaa2f34e4714b16ca65ff79da63b72d962f7
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
Allow a debug server such a GDB to take control when a fatal error
occurs. The debug server simply has to define a _debug_fatal_hook()
function that will override the weak function installed by default.
Change-Id: Ib9dca5755868f747b697fa3178e09109f1eedb07
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
Quark flash sub-driver. It is based on the QMSI driver.
In order to enable this driver, the following options
must be set.
CONFIG_QMSI_DRIVERS
CONFIG_QMSI_INSTALL_PATH
CONFIG_FLASH
CONFIG_SOC_FLASH_QMSI
Origin: Original
Change-Id: Iffbea3b17624c755e367677b76d7216c2fba2ca1
Signed-off-by: Baohong Liu <baohong.liu@intel.com>
The D2000 CRB is similar to the Arduino 101 (at least as GPIO is
concerned). Add support for using the GPIO controller without QMSI
libraries.
Change-Id: I001da05c9a9d5771b2ec678a9d4a91c44db05289
Signed-off-by: Vlad Dogaru <vlad.dogaru@intel.com>
Remove those kconfig options that are SoC specific, and
should not be configurable via kconfig.
Change-Id: Ib483419be5199b52cf281b4b106cd8a3be95b7be
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Remove UART default configuration to make it default UART_0. This
makes default working fine with Nordic BLE chip using H:4 driver.
Change-Id: Icb6d9f068b586bbf04694bc77ed968211de94c8a
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Allow to connect Nordic Devkit or dongle to qemu. Simple
configuration for the current NBLE firmware is following:
Connect Nordic board to PC, ttyACMX gets created.
$ socat -x /dev/ttyACMX,raw,b1000000 unix-listen:/tmp/bt-server-bredr
Build app with prj_nble.conf and run with make qemu
Change-Id: I354644b465ad09ab0ca62fbd97f15d9bb3c87d6a
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Remove those kconfig options that are SoC specific, and
should not be configurable via kconfig.
Change-Id: Ib7e0b81b2df1a0225fc244fea3035416d0a4f282
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Remove those kconfig options that are SoC specific, and
should not be configurable via kconfig.
This also separates IRQ_PRI into one for DW and one
for QMSI, to follow the convention of every other
drivers.
Change-Id: I338f819f71c18fa9e17015e8a588a3d0207350c6
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Remove those kconfig options that are SoC specific, and
should not be configurable via kconfig.
Change-Id: Ic73783189db57059d2b7f3727e4802e1b2e27931
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Remove those kconfig options that are SoC specific, and
should not be configurable via kconfig.
Change-Id: Ifdbb5e3a997795ef577350d88f8cb06877eb6463
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Remove those kconfig options that are SoC specific, and
should not be configurable via kconfig.
Change-Id: Ib8158f00a6c6616360ddbcf63981f1a85911c1b9
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
This patch extends the i2c shim driver so it supports the 'default
configuration' infrastructure which enables the user to specify a
default configuration for the I2C device. The default configuration
is set during driver initialization.
This patch also changes Quark SE and D2000 Kconfig.defconfig files so
the i2c default configuration is set to '0x12' which means standard
bus speed, 7-bit addressing and master mode. This is the same value
used when DW driver is selected, by the way.
Change-Id: I06e0dc3c29e8da2f3317db5bef285177f2e92c9a
Signed-off-by: Andre Guedes <andre.guedes@intel.com>
Remove those kconfig options that are SoC specific, and should not be
configurable via kconfig.
Change-Id: Ia62888838877da4627419bd36c261d5254761acd
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
It wasn't correct to add the size of the long jump instruction
as it *replaces* a short jump instead of just being after it.
So redefine this to be the difference in size between these
two instructions.
Change-Id: I65be2afab19d9cd8b096551acde0156f0503df87
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
These interrupt settings are SOC specific. So, move them to the
SOC level of Kconfig.
As IRQ priority is fixed in D2000, changed the value to 0 to
make it consistent with what other shim drivers are using.
Change-Id: Id20bed46c478a7555ae976e3a3063ba2cb099788
Signed-off-by: Baohong Liu <baohong.liu@intel.com>
This is hardware design so there is no need for it to be
configurable in kconfig.
Change-Id: Iff162f330aae8ef9a7139b6e7ed9bfa87f26189a
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
There is no need to re-define CONFIG_UART_CONSOLE_ON_DEV_NAME to be
"UART_0" all over the place as its default is "UART_0" already.
So remove those duplicate defaults.
Change-Id: Ia86e26b8f90540fdbd7dcb3358d6dac352648b21
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
The IRQ triggering condition should be specified by SoC as it is
a decision for hardware design. This should not be configurable
in kconfig.
The default is to be triggered on rising edge, just as the same
old kconfig did.
Change-Id: If59d88a30711eb8e03d9cc4f409055cefe1995c5
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Moves those kconfig options which should be declared in
SoC or board header files instead. These are the one
that are tied to SoC or board and there is no need
for them to be configurable in kconfig.
Change-Id: I243d634f1a4a11dc8dc3530d95f93371015492b7
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
This is to standardize the kconfig for specifying IRQ priority.
Change-Id: Iab10655c6fc6f17c0c6dd49cb7a4e74fabcf852c
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
This is to standardize the kconfig for specifying IRQ priority.
Change-Id: I3a51b35e633dc7b1b841e9fa504bf0cfc0d4d575
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Most of the SoC and board Kconfig use the same values for
driver initialization priorities. So refactor them, and
discard duplicate ones.
The shared IRQ init priority was changed so that the kernel
default init and device init priorities can be standardized
across all SoC/boards. Same goes for DesignWare SPI driver.
This also changes the UART_CONSOLE_PRIORITY and
IPM_CONSOLE_PRIORITY to UART_CONSOLE_INIT_PRIORITY and
IPM_CONSOLE_INIT_PRIORITY, to standardize across all drivers.
Note that this does not take away the ability to override
those values. This just provides reasonable defaults such
that there is virtually no need to override.
Change-Id: Ibbd95d802c637df06f9a2fd48763ee1e6f4ff627
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
The pinmux base address and number of pins are now defined in SoC or board
header files instead of specifying them in kconfig. This is because
the pinmux ties directly to the SoC (or board expanders) so the base
address and number of pins do not need to be configurable in kconfig.
Change-Id: Ib6090d7d022b491f3fe8f522858281504c6302bb
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
This adds conditions to the default values for device init priorities,
and make them follow the dependencies on the config options. This cleans
up the resulting .config a bit, making it easier to read.
Change-Id: Ib05806ac6108d465ffe245142ecca7a51be6df22
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
There are two major issues with the kconfig:
() Some of the config options have incorrect dependencies inside help
under menuconfig. For example, CONFIG_GPIO depends on BOARD_GALILEO.
() Since the SoC and board specific kconfig files are parsed first,
the help screen would say, for example, CONFIG_SPI is defined at
arch/arm/soc/fsl_frdm_k64f/Kconfig. This is incorrect because
the actual config is defined in drivers/spi/Kconfig.
These cause great confusion to users of menuconfig/xconfig.
To fix these, the SoC and board defaults are now to be parsed last.
Note that the position swapping of defaults in this patch is due to
the fact the the default parsed last will be used.
And, spi_test is broken due to the fact that it requires
CONFIG_SPI_INTEL_PORT_1, but never enables it anywhere. This is
bypassed for now.
Origin: refactored and edited from existing files
Change-Id: I2a4b1ae5be4d27e68c960aa47d91ef350f2d500f
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Changed names of Kconfig flags, variables, functions, files and
return codes consistent with names used in the RFC. Updated
relevant comments to match the changes.
Origin: Original
Change-Id: Ie7941032d7ad7af61fc02928f74538745e7966e8
Signed-off-by: Ramesh Thomas <ramesh.thomas@intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
This patch replaces all occurrences of DEV_* codes by errno.h codes at
the arch layer.
Change-Id: I1a1ab6d0481f3660ad032e2690d2577245fe1f34
Signed-off-by: Andre Guedes <andre.guedes@intel.com>
This patch fixes the QMSI UART shim driver so we are able to use it in
Quark D2000 based platforms. Differently from Quark SE, the peripheral
clock gate bit (CLK_PERIPH_CLK) is not enabled by default in Quark
D2000. We have to explicitly set this bit in order to properly initialize
the device.
Since this drivers is now properly working on Quark D2000, this patch
also sets the QMSI driver default options in arch/x86/soc/quark_d2000/
Kconfig.
Change-Id: I817b7703554be162ac628dcd8d3d07512b9eb3f5
Signed-off-by: Andre Guedes <andre.guedes@intel.com>
() Moves the Quark SE clock control into its submenu.
() Fixes the dependencies in the SoC default Kconfig
so the options are not displayed out of place in
menuconfig.
Change-Id: Ifdf06242be8ceed03c2c657c942875a5a7f2750e
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
The SoC selections for each architecture are moved to the top level
in menuconfig and xconfig. This makes it more intuitive to select
architecture -> SoC -> then board, avoiding an additional trip to
go into the architecture menu to select SoC.
Change-Id: I57a78a09adfc4bb12423915b6ad14ceb74381a2b
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
It makes no sense to allow enabling support for floating point
registers when the CPU has no FPU.
Change-Id: If51187033fc84957721d87fa6e79ef31124f4b14
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
These options should be selected by individual SoC automatically,
and should not be visible options. Or else it would be possible to
select Quark SoCs and telling Kconfig it is from Atom family (which
is incorrect).
Change-Id: I17a6cf713378333e0e7942aa49b381b5eb9526b5
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
When building with IAMCU, make sure we set the soft-float, otherwise
build would fail with unsupported instruction errors.
JIRA: ZEP-103
Change-Id: I7a5f107a2df50799a7f6dd4aba36c1a977c1461d
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
This creates the QMSI comparator driver which is simply a shim driver
based on the comparator driver provided by QMSI BSP.
In order to enable this driver, the following options should be set:
CONFIG_QMSI_DRIVERS=y
CONFIG_QMSI_INSTALL_PATH="/path/to/libqmsi/directory"
CONFIG_AIO_COMPARATOR=y
CONFIG_AIO_QMSI_COMPARATOR=y
Origin of the file: Original
Change-Id: Iad01cb80f7bb1eff1710cd76cd0afeb70c311e04
Signed-off-by: Sergio Rodriguez <sergio.sf.rodriguez@intel.com>
This patch extends the UART QMSI driver so it supports the IRQ APIs from
include/uart.h. The IRQ APIs are enabled by the 'CONFIG_UART_INTERRUPT_
DRIVEN' option.
Differently from others APIs such as I2C and SPI, the UART API is very
low level. For that reason, the IRQ facilities (e.g. irq based transfers)
from the QMSI driver are not useful to the shim driver at the moment. In
order to implement the IRQ APIs we rely on UART registers defined by QMSI.
QMSI UART header is missing some macro definitions from IRR register so
we define them in the shim driver.
Since the IRQ trigger condition is not configurable in the QMSI shim
driver, this patch also changes drivers/serial/Kconfig so the "UART
IRQ Trigger Condition" choice doesn't appear on the menu if the QMSI
driver is selected.
Change-Id: Idf9a0f6a47af2a550a31f474d721068dca989713
Signed-off-by: Andre Guedes <andre.guedes@intel.com>
This patch introduces the QMSI UART driver which is simply a shim driver
based on UART driver provided by QMSI BSP.
This initial version implements only the mandatory APIs 'poll_in',
'poll_out' and 'err_check' which are required by trivial sample apps and
by output functionality from the console driver. The remaining APIs will
be implemented by up coming patches. The driver supports only 115200 baud
rate at the moment.
In order to enable this driver, the following options should be set:
CONFIG_QMSI_DRIVERS=y
CONFIG_QMSI_INSTALL_PATH="/path/to/libqmsi/directory"
CONFIG_SERIAL=y
CONFIG_UART_QMSI=y
This driver has been tested with Quark SE Devboard so this patch also
adds its platform-specific default configuration options to 'arch/x86/
soc/quark_se/Kconfig'.
Change-Id: Ibde1825d4b0349a376a8e7d91cc9de306946b62f
Signed-off-by: Andre Guedes <andre.guedes@intel.com>
The thread monitor allows to iterate over the thread context
structures for each existing thread (fiber/task) in the system.
Thread context structures do not expose thread entry information
directly. Although all the information can be scavenged from memory
stacks. Besides, accessing the information depends on the stack
implementation for each architecture.
By extending the tcs we allow a direct access to the thread
entry point and its parameters, only when thread monitor is
enabled.
It also allows a task to access its kernel task structure
through the first parameter of the thread.
This allows a debugger application to access the information directly
from the thread context structures list.
Change-Id: I0a435942b80eddffdf405016ac4056eb7aa1239c
Signed-off-by: Juan Manuel Cruz <juan.m.cruz.alcaraz@intel.com>
This patch removes the macro UART_IOAPIC_FLAGS from Quark SE and D2000
soc.h since it is not used anywhere in the code.
Change-Id: I0fd42fac2f02e8617bd92c73c1a0354ef2d7a71a
Signed-off-by: Andre Guedes <andre.guedes@intel.com>
One of the tricks that GCC's stack protector does is to stick a
sentinel value on the stack at the beginning of the function, and
check if it is still there when the function is about to return.
However, since this function switches stacks that fails and we get
a stack protector exception before main() even starts.
Change-Id: I2acba8b8c822d7447d8e371bb72603f36e87f54b
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Remove CPU_MIGHT_SUPPORT_CLFLUSH as excessive.
Removal the flag requires adding per-SoC cnfiguration,
as some Quark models support clflush instruction, but
some do not, even on compiler level.
Change-Id: I655cba00c629db55d1813c199a2fe08b2d60ef4f
Signed-off-by: Dmitriy Korovkin <dmitriy.korovkin@windriver.com>
Rearrange the source code in order to place functions
depending on clflush support detection into the proper
section.
Removed dependency between CACHE_LINE_SIZE_DETECT and
CLFLUSH_INSTRUCTION_SUPPORTED or CONFIG_CLFLUSH_DETECT.
Change-Id: I62ba5199763ed16c71f1d2fa372f6cc99b303e6a
Signed-off-by: Dmitriy Korovkin <dmitriy.korovkin@windriver.com>
The peripherals utilizing UART were required to register their own
ISR rountines. This means that all those peripherals drivers need
to know which IRQ line is attached to a UART controller, and all
the other config values required to register a ISR. This causes
scalibility issue as every board and peripherals have to define
those values.
Another reason for this patch is to support virtual serial ports.
Virtual serial ports do not have physical interrupt lines to
attach, and thus would not work.
This patch adds a simple callback mechanism, which calls a function
when UART interrupts are triggered. The low level plumbing still needs
to be done by the peripheral drivers, as these drivers may need to
access low level capability of UART to function correctly. This simply
moves the interrupt setup into the UART drivers themselves. By doing
this, the peripheral drivers do not need to know all the config values
to properly setup the interrupts and attaching the ISR. One drawback
is that this adds to the interrupt latency.
Note that this patch breaks backward compatibility in terms of
setting up interrupt for UART controller. How to use UART is still
the same.
This also addresses the following issues:
() UART driver for Atmel SAM3 currently does not support interrupts.
So remove the code from vector table. This will be updated when
there is interrupt support for the driver.
() Corrected some config options for Stellaris UART driver.
This was tested with samples/shell on Arduino 101, and on QEMU
(Cortex-M3 and x86).
Origin: original code
Change-Id: Ib4593d8ccd711f4e97d388c7293205d213be1aec
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Clockgating was disabled for RTC and disabling RTC had no
effect on Quark SE boards.
Change-Id: I67448d5582a206fc7a68d763d504e9f743043b53
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
ia32/soc.h is only used by QEMU, but QEMU's INTx routing does not follow
the "standard design consideration".
Instead, the pins are swizzled based on the PCI slot. They are then
routed to IRQs based on the PIIX PIRQ configuration.
For simplicity use hard-coded values for the PIIX PIRQ configuration,
though it may be desirable in the future to determine these dynamically.
Also change the number of PCI buses to 1 and remove irrelevant comments.
Change-Id: I1592009a43dd8a9c5a7c54788fba52f14687ba35
Signed-off-by: Ido Yariv <ido@wizery.com>
The app-facing interface for configuring interrupts was never
formally defined, instead it was defined separately for each arch
in their respective arch-specific header files. Occasionally these
would go out of sync.
Now there is a single irq.h header which defines this interface.
To avoid runtime overhead, these map to _arch_* implementations of
each that must be defined in headers pulled in by arch/cpu.h.
Change-Id: I69afbeff31fd07f981b5b291f3c427296b00a4ef
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
That implementation is not galileo-specific, but rather a generic way of
rebooting an x86 target. Needs SoC support.
Change-Id: I9c3374a8ab57a624d9d9b7090260c5b11fe4e773
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
This patch removes the default value from some platform/SoC specific
options which are declared in drivers/i2c/Kconfig because 1) most of
the time they are not valid values and 2) the correct values are
already set in the SoC Kconfig.
It also moves the interrupt priority definition from the driver's
Kconfig to the platform's Kconfig since it is a platform-specific
configuration.
Change-Id: If3c260b9a2fa095de47a99eb7fa5b947efefe9b1
Signed-off-by: Andre Guedes <andre.guedes@intel.com>
This patch removes the default value from some platform/SoC specific
options which are declared in drivers/spi/Kconfig because 1) most of
the time they are not valid values and 2) the correct values are
already set in the SoC Kconfig.
It also moves the interrupt priority definition from the driver's
Kconfig to the platform's Kconfig since it is a platform-specific
configuration.
Change-Id: Ic992749b3210ed8a2e454edece41ceca5edbaf2e
Signed-off-by: Andre Guedes <andre.guedes@intel.com>
This patch removes the default value from some platform/SoC specific
options which are declared in drivers/gpio/Kconfig because 1) most of
the time they are not valid values and 2) the correct values are
already set in the SoC Kconfig.
It also moves the interrupt priority definition from the driver's
Kconfig to the platform's Kconfig since it is a platform-specific
configuration.
Change-Id: Id00f7907fa55025011dabce6e282a9623be23831
Signed-off-by: Andre Guedes <andre.guedes@intel.com>
This patch fixes the QMSI SPI shim driver so we are able to use it in
Quark D2000 based platforms. The only change required to enable this
driver is an #if guard in spi_qmsi_init() because the macro QM_SPI_MST_1
and the function qm_spi_master_1_isr are not defined in QMSI headers
from Quark D2000.
Since this drivers is now properly working on Quark D2000, this patch
also sets the QMSI driver default options in arch/x86/soc/quark_d2000/
Kconfig.
Change-Id: Ic6e2f7f5a2c3f350ddf360b23ffab6b812948572
Signed-off-by: Andre Guedes <andre.guedes@intel.com>
This patch removes the default value from some platform/SoC specific
options which are declared in drivers/watchdog/Kconfig because 1) most
of the time they are not valid values and 2) the correct values are
already set in the SoC Kconfig (e.g. arch/x86/soc/quark_d2000/Kconfig).
For Quark D2000, the IRQ priority options (WDT_DW_IRQ_PRI and WDT_QMSI_
IRQ_PRI) values are set to '0' since the priority information is ignored
by the interrupt registering system (the interrupt vectors are fixed in
this SoC).
Change-Id: I8f36c0f0e56211cdee3f2c6fc90c7dcac0a1b5aa
Signed-off-by: Andre Guedes <andre.guedes@intel.com>
This patch removes the default value from some platform/SoC specific
options which are declared in drivers/rtc/Kconfig because 1) most of
the time they are not valid values and 2) the correct values are
already set in the SoC Kconfig (e.g. arch/x86/soc/quark_d2000/Kconfig).
For Quark D2000, the RTC_IRQ_PRI default value is set to '0' since the
priority information is ignored by the interrupt registering system
(the interrupt vectors are fixed in this SoC).
Change-Id: I70de889cfd22e65f0e7acf7e57ddc6439f028394
Signed-off-by: Andre Guedes <andre.guedes@intel.com>
The name already set by the driver's Kconfig is correct, so overriding
it only causes confusion.
Change-Id: Ia6405786fdfdf103c922517c8140a07a9de387e0
Signed-off-by: Vinicius Costa Gomes <vinicius.gomes@intel.com>
This patch fixes the GPIO QMSI shim driver so we are able to use it in
Quark D2000 based platforms. To enable this driver we have to add a few
#if guards because some macros and functions (e.g. QM_AON_GPIO_0 and
qm_aon_gpio_isr_0) are not defined in QMSI headers from Quark D2000
(this SoC doesn't support the Always-On GPIO controller).
This patch also adds the QMSI driver default options to arch/x86/soc/
quark_d2000/Kconfig.
Change-Id: Ia16a345e1de3008f167ed66f891834607c05f4a2
Signed-off-by: Andre Guedes <andre.guedes@intel.com>
This adds support to the AON GPIO controller using the QMSI driver.
In order to enable it, the following configuration options must be set:
CONFIG_QMSI_DRIVERS=y
CONFIG_QMSI_INSTALL_PATH="PATH TO LIBQMSI"
CONFIG_GPIO_QMSI=y
CONFIG_GPIO_QMSI_AON=y
Change-Id: I5a1a232d97741ad7fdbf40d8aea5a835e5b4e724
Signed-off-by: Vinicius Costa Gomes <vinicius.gomes@intel.com>
This adds a NULL check against the reset vector for ARC.
If the reset vector is null, do not start the ARC core
as there is nothing to execute, and will probably cause
the whole SoC to stall.
Change-Id: I78d77b3e5940a205e05c13369f889cf9c5955487
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
This patch changes both Quark SE and D2000 Kconfig files to enable the
WDT_DW driver by default if the WATCHDOG is enabled. This way, we keep
it consistent with the approach we already follow for others peripheral
drivers (GPIO, I2C, SPI).
Change-Id: I9d8b81c0e659b1408137deb71e33dacf6d4108c2
Signed-off-by: Andre Guedes <andre.guedes@intel.com>
This patch changes both Quark SE and D2000 Kconfig files to enable the
RTC_DW driver by default if the RTC is enabled. This way, we keep it
consistent with the approach we already follow for others peripheral
drivers (GPIO, I2C, SPI).
Change-Id: I4910e501c105b6218d046080c47b1e7a42eced92
Signed-off-by: Andre Guedes <andre.guedes@intel.com>
This patch fixes the QMSI I2C shim driver so we are able to use it in
Quark D2000 based platforms. The only change required to enable this
driver is an #if guard in i2c_qmsi_init() because the macro QM_I2C_1
is not defined in QMSI headers from Quark D2000.
Since this drivers is now properly tested with Quark D2000, this patch
sets the QMSI driver default options in arch/x86/soc/quark_d2000/Kconfig.
It also adds the wiring information required to test the i2c_lsm9ds0
sample app in the Quark D2000 CRB.
Change-Id: I4be03c09304da5a66ac663e48b1d72225eb5651d
Signed-off-by: Andre Guedes <andre.guedes@intel.com>
In case the I2C_QMSI driver is selected by the user, enable both I2C
contollers by default. This is the default behavior for I2C_DW driver
as well.
Change-Id: If3dc8eb0a266fde7f598f7b12370e5be903aafed
Signed-off-by: Andre Guedes <andre.guedes@intel.com>
Always use braces, even on one-line code blocks.
Change-Id: Ic9e60db7f851d2fbee5bfd79cd810df23c0c5db0
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
This is part of an ongoing development of power management
support in zephyr. This implementation builds upon an existing
hook interface and adds more enhancements. This was tested
with reference implementations on quark_d2000 and quark_se.
Change-Id: I28092b7ec90ce1f1cc661cf99ca88708910c8eb2
Signed-off-by: Ramesh Thomas <ramesh.thomas@intel.com>
Renamed functions and labels used in power management code
according to coding convention. Only doing this to relevant
functions and not touching functions that will be removed in
future patches.
The stack used during resume would be necessary so
renamed that too.
Change-Id: I2f09a349b0f0fd6520c11b4cd73f4c8e1a13f100
Signed-off-by: Ramesh Thomas <ramesh.thomas@intel.com>
GlobalTss is not defined anywhere. This was originally designed
to be used by power management code to switch thread context to
kernel resume location. An alternative to this method would be
implemented.
Change-Id: I9ae14ba14f9573d8bd8579869cdee9cf85a5684a
Signed-off-by: Ramesh Thomas <ramesh.thomas@intel.com>
Modifications to timer drivers and interrupt setup, to manage
the tickless idle for the x86 architecture
Change-Id: Ie02d484b7e5636de6ea382ba2eeed57e704c8498
Signed-off-by: Sergio Rodriguez <sergio.sf.rodriguez@intel.com>
Looking at the IDT in a debugger is confusing, add a pretty-printing
function.
Change-Id: Iacc5e204e5d11e3e875c75ddf6d2e2e80b230299
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
It was, in a nutshell, wrong. Fortunately, the incorrectly
specified fields weren't being used by anything.
Change-Id: I0fa63fa16a267502744a7a2c82865c7de8b5446e
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
DEBUG isn't tied to any config option. Just use assertions.
Most of the time return values aren't being checked anyway.
Change-Id: I7457dcf00e18505bd6bcd98d46288545c03b5fbc
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Having priority levels 0 and 1 reserved on x86 due to implementation
details on how the CPU uses the vector table is confusing to users,
and makes it unnecessarily difficult to share drivers between arches.
Now on x86, priority levels 0 and 1 are available. Semantically, all
priority levels have had 2 subtracted from them.
It is no longer necessary to specify a priority level when the
vector itself is specified. If an IDT entry has a specific vector
associated with it, any priority argument is simply ignored.
In gen_idt, some simplifications have been made:
- The printed representation of a generated entry now fits on one line
- Some checks being done in validate_priority() were redundant, as
generate_interrupt_vector_bitmap() also ensures that there are
sufficient free vectors within a priority level.
Change-Id: I26669d8ee0a53f48fbc2283490a8c42d8b1daf8e
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
The argument to _common_dynamic_exc_handler() in the C domain
was still being set up the Sys V way. Arguments are popped off the
stack in reverse order, so _ExcEnt pushes *pEsf for arg 2, and then
the stub pushes the stub_num for Arg 1.
For IAMCU case, *pEsf is placed in EAX which is where argument 1
lives; static exception handlers take just one argument. However
since we're calling _common_dynamic_exc_handler we also need to
supply the stub_id, which we put in EDX (where arg 2 goes).
Rather than swapping things around at runtime the prototype for
_common_dynamic_exc_handler() is adjusted to fit the calling
convention in use.
Change-Id: Id43cbc3b86d90f941cea771678b2796ae5f1358d
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Adds logger support to iamcu core for the following features:
- context switch logger
- interrupt logger
- sleep logger
Change-Id: Icfbd5fa787633045ba2895e8c28b652c55575b86
Signed-off-by: Juan Manuel Cruz <juan.m.cruz.alcaraz@linux.intel.com>
The common stub code didn't prefix the arg to 'mov' with a
'$', causing the assembler to generate code which tries to
dereference the argument before sticking it in EAX.
Change-Id: I0e201f799565d9709e3969b82ae2eb3f93a78b3a
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
The ASM stub invoked by irq_offload() wasn't switching to the
interrupt stack.
Change-Id: I0c52092a50396aa892e71f0501bbda38395d7554
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Making pipe driver configuration for quark_se makes no sense for the
board. First it simply wrong since IRQs for serial are 5 and 6 and
when using PIPE care should be taken to allocate right way serial and
Bluetooth for the given UARTs.
Change-Id: I4cb3227a8be34fbfa089a457e6d9977e4adcfd19
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
QUARK_SE_IPM_CONSOLE_RING_BUF_SIZE32 symbol must be editable through
configuration menus and configuration snippets (QA request).
Adding a title for the kconfig symbol makes it editable.
Change-Id: Id0147a50d94033e1392327935bcbfbdb5a9eedd8
Signed-off-by: Juan Manuel Cruz <juan.m.cruz.alcaraz@linux.intel.com>
This driver uses the QMSI library and mostly translates calls from the
Zephyr API to QMSI ones.
This driver conflicts with the native driver implemenation. In order to
enable it, you must set:
CONFIG_QMSI_DRIVERS=y
CONFIG_QMSI_INSTALL_PATH="PATH_TO_QMSI"
CONFIG_SPI_QMSI=y
CONFIG_SPI_QMSI_PORT_0=y
CONFIG_SPI_QMSI_PORT_1=y
Missing:
- Support for using a GPIO pin as Chip Select;
Change-Id: I0d8eca88a2a803b6b3604f396f874313fe90753c
Signed-off-by: Vinicius Costa Gomes <vinicius.gomes@intel.com>
Decisions on compiler optimizations were done on the architecture level,
this does not scale and some SoCs will have different optimization levels
or compiler options needed. Moving this to the SoC makes it easy to optimize
differently when using the same CPU which we use to set the right optimization
now on the architecture level.
For IAMCU platforms, use the right architecture and tuning.
-march=lakemont -mtune=lakemont -miamcu -msoft-float
Change-Id: I458afca5feb9be5de8dcae559d6dcac3c6d6a2a7
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Due to an issue with the interrupt-based transfer API from QMSI driver,
the 'transfer' callback from the shim driver (i2c_qmsi_transfer) is
implemented with polling APIs. This is not ideal because we are not able
to sleep the current thread (so another task can be scheduled in) while
the i2c operation is carried out.
The interrupt issue with the QMSI driver has been solved then this patch
fixes the shim driver so it uses the interrupt-based API and adds extra
code to handle the thread synchronization.
Finally, this patch also moves all 'struct device' related definitions
from the bottom to the top of the i2c_qmsi.c file so the DEVICE_GET
macro can be used in transfer_complete() and removes the init.h include
since it is not needed anymore.
Change-Id: I7ef7ce4cea6fcc939e310e5fe12c406645f6a16e
Signed-off-by: Andre Guedes <andre.guedes@intel.com>
IRQAGENT3 is initialized explicitly, but IRQAGENT0 isn't and its value
is based on the value the BIOS or bootloader had set before. Fix this by
explicitly initializing IRQAGENT0, and swizzle the IRQs to reduce
conflicts.
Update the pci_pin2irq function to accommodate for these changes.
Also remove pci_irq2pin function since it is unused.
Change-Id: I7b1dfc7659ab227fe66711a3af5a1f34fd4a7972
Signed-off-by: Ido Yariv <idox.yariv@intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Signed-off-by: Ido Yariv <ido@wizery.com>
To debug PCI drivers on QEMU, it may be desired to enable CONFIG_PCI for
QEMU targets. Since the PCI driver requires a SOC pin2irq translation
function, add such function to IA32's SOC header file.
Change-Id: Icf6f88aa14ae29d70fe12dc80a708e6a2e992ba8
Signed-off-by: Ido Yariv <idox.yariv@intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Signed-off-by: Ido Yariv <ido@wizery.com>
We don't normally need a runtime-mutable GDT; make it optional to
activate a second copy in RAM. Regardless of whether it is in RAM
or ROM, it can be accessed by the '_gdt' symbol.
Change-Id: I5ce955f4b8875eb60040917ceaacc07d7e5941ac
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Move BLE configuration to board and enable GPIO for NBLE.
Change-Id: I99c309656430936edf6766fc99fe83b011801bb4
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Adds basic support for communication with Nordic BLE (NBLE) chip
connected to UART.
Change-Id: I3651e291ec18805a63ecd3d240dce62273e3c498
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
It's not a function and requires all its arguments to be build-time
constants. Make this more obvious to the end user to ease confusion.
Change-Id: I64107cf4d9db9f0e853026ce78e477060570fe6f
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Mostly SoC initialization and some kernel subsystems, but also some
device drivers like the interrupt controllers.
Change-Id: I8dc1844c33acd877c075b6b03558fdca6f87500b
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
This is the last step before obsoleting DEVICE_DEFINE() and
DEVICE_INIT_CONFIG_DEFINE().
Change-Id: Ica4257662969048083ab9839872b4b437b8b351b
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
Rename it to DEVICE_DEFINE() so that it fits in the 'device' namespace.
Change-Id: I3af3a39cf9154359b31d22729d0db9f710cd202b
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
Most systems have far less than 256 IRQ lines available, so
save some bytes in ROM by making this a config option.
On systems with MVIC, omit the table entirely as the mapping
is fixed.
The build cmd_gen_idt is slightly easier to read and will fail
immediately if any of the commands in the sequence error out.
Change-Id: I411f114557591e5cd96b618e6f79f97e8bedadf0
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Rename it to DEVICE_INIT_CONFIG_DEFINE(), because (a) it was not fitting
in any namespace and (b) it is not used to declare, but rather define a
object.
Change-Id: I1da5822f06b85a9fb024b5b184afd0ccc01012ec
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
This bitfield is only needed to find unused vectors in the IDT
for installing dynamic interrupts.
Change-Id: I34ecd330774a0e50f240b4396527682eded29627
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Fix an issue where, if a task is pending on a nano timeout, the duration
it wants to wait is not taken into account by the tickless idle code.
This could cause a system to wait forever, or to the limit of the timer
hardware (which is forever, for all intents and purposes).
This fix is to add one field in the nanokernel data structure for one
task to record the amount of ticks it will wait on a nano timeout. Only
one task has to be able to record this information, since, these waits
being looping busy waits, the task of highest priority is the only task
that can be actively waiting with a nano timeout. If a task of lower
priority was previously waiting, and a new task is now waiting, it means
that the wait of the original task has been interrupted, which will
cause said task to run the busy loop on the object again when it gets
scheduled, and the number of ticks it wants to wait has to be recomputed
and recorded again.
Change-Id: Ibcf0f288fc42d96897642cfee00ab7359716703f
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
Adds C++ support to the build system.
Change-Id: Ice1e57a13598e7a48b0bf3298fc318f4ce012ee6
Signed-off-by: Dmitriy Korovkin <dmitriy.korovkin@windriver.com>
Signed-off-by: Peter Mitsis <peter.mitsis@windriver.com>
Adds extern "C" { } blocks to header files so that they can be
safely used by C++ source files.
Change-Id: Ia4db0c36a5dac5d3de351184a297d2af0df64532
Signed-off-by: Peter Mitsis <peter.mitsis@windriver.com>
Introduce the GPIO QMSI-based implementation. This is basically a
shim layer that implement's Zephyr's GPIO APIs on top of QMSI drivers.
This is an alternative driver that conflicts with the previous
GPIO_DW implementation. In order to enable it you must set:
- CONFIG_GPIO=n
- CONFIG_GPIO_QMSI=y
- CONFIG_GPIO_0=y
- CONFIG_QMSI_DRIVERS=y
- CONFIG_QMSI_INTALL_PATH="PATH_TO_QMSI"
Note that this driver currently only supports one controller instance,
GPIO_0. It is implemented this way due to a limitation from the current
version of QMSI. QMSI versions later than 1.0 doesn't have this
limitation.
Missing:
- support multiple controller instances (gpio_0, gpio_1, etc);
- enable level triggered interrupts in sync with system clock,
through setting INT_CLOCK_SYNC properly.
Change-Id: Ib61b153dae9741806a9a31d7dc1f82b96d000fbe
Signed-off-by: Jesus Sanchez-Palencia <jesus.sanchez-palencia@intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Signed-off-by: Vinicius Costa Gomes <vinicius.gomes@intel.com>
It wasn't immediately clear in _execute_handler() that
enable_interrupts() didn't actually do anything if
CONFIG_NESTED_INTERRUPTS wasn't enabled.
If we are not using nested interrupts, perform small optimization
1) The call to disable interrupts isn't necessary as interrupts
are already disasbled
2) The check for !_nanokernel.nested in a couple places always
evaluates to true if nested interrupts aren't used
Change-Id: I7e66cee0466d03bc1172a572e19389accf6e0e62
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
On Quark SE, SPI might require GPIO to be ready before hand, to emulate
CS, thus providing an option to tweak the intialization priority for SPI
DW driver.
Change-Id: Ifa373948ac8227bf6e4ed1113bcb4dc9139b6663
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
Quarks SE owns a GPIO controller which is always on (so not clock-gated)
thus providing it base address, the pins it handles etc...
Change-Id: Ifceb7cb74e763a91130d615ba19756ddcbe97a23
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
This is valid only for Quark SE and Quark SE SS, where it requires to
unmask the interrupt for each specific controller. Thus making the
function generic, using the parameter as the specific mask base address.
Change-Id: Iea0a412b8d94a1ab5e1f3e339eaf632eacee5797
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
The original value of 128 was selected more or less randomly, and
isn't sufficiently large enough for QA needs.
Change-Id: I8a9fcc86d6b5fa7dc5ba05896c62f7dd608f9ed2
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
This reverts commit 778d5b11c5327be4b40c7745e9beaecfd6327e13.
This patch has been identified as breaking the build when trying
to manually build non-x86 applications.
Change-Id: I1857745049dfef7193de58737108314b7aae01c5
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
This option misunderstands how XIP works. The IDT is ALWAYS in ROM,
the question is whether crt0 will copy it into RAM or not. You can't
save ROM space in this way.
Change-Id: I58025e3d71ead35730d0a5026213299b4fcb5eb9
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
These are not (yet) used anywhere and generate unnecessary warnings.
Just remove them.
Change-Id: Ibae472c4a639466c221cdc354232780db04e963e
Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
Define configuration for Nordic chip connected to UART0.
Change-Id: Ia6007def747932e5f9fbd57f1ea8005892a2f793
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Decisions on compiler optimizations were done on the architecture level,
this does not scale and some SoCs will have different optimization levels
or compiler options needed. Moving this to the SoC makes it easy to optimize
differently when using the same CPU which we use to set the right optimization
now on the architecture level.
For IAMCU platforms, use the right architecture and tuning.
-march=lakemont -mtune=lakemont -miamcu -msoft-float
Change-Id: I0f77cffe7a139f8b2620935094437d0dfd160dfe
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
The Kbuild system first looks for a Kbuild file, then it looks for
a make file.
Use the Kbuild for object building and leave the Makefile for definding
build options and compiler flags and other SoC related defines.
Change-Id: I0be59bb5ae02a29108a188efbd6f14dcdb7de4ee
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
The interrupt API has been redesigned:
- irq_connect() for dynamic interrupts renamed to irq_connect_dynamic().
It will be used in situations where the new static irq_connect()
won't work, i.e. the value of arguments can't be computed at build time
- a new API for static interrupts replaces irq_connect(). it is used
exactly the same way as its dynamic counterpart. The old static irq
macros will be removed
- Separate stub assembly files are no longer needed as the stubs are now
generated inline with irq_connect()
ReST documentation updated for the changed API. Some detail about the
IDT in ROM added, and an oblique reference to the internal-only
_irq_handler_set() API removed; we don't talk about internal APIs in
the official documentation.
Change-Id: I280519993da0e0fe671eb537a876f67de33d3cd4
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Currently, if we disable I2C_DW through 'menuconfig', I2C_DW_0* and
I2C_DW_1* options are not disabled even if they depend on I2C_DW
option. This makes the menuconfig confusing and we end up with the
wrong config set in .config file:
...
CONFIG_I2C_DW is not set
CONFIG_I2C_DW_0=y
...
CONFIG_I2C_DW_1=y
...
This patch fixes this issue by surrounding the I2C_DW_0* and I2C_DW_1*
options with 'if I2C_DW'.
Change-Id: I7e949b066425bca2533f8b84b9ea7b1915369ff0
Signed-off-by: Andre Guedes <andre.guedes@intel.com>
On SysV ABI, the NANO_ESF parameter is passed in via the stack.
For IAMCU, this is instead expected to be in EAX.
_ExcEnter is currently using EAX to stash the return address of
the calling stub while it does a stack switch. Change it to use ECX
for this purpose, and if we are running with IAMCU place the
parameter in EAX instead of pushing it.
The output of the fault handler has been cleaned up a bit and it
now also includes the code segment.
Change-Id: I466e3990a26a1a82dd486f3d8af5395eab60b049
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
This was never implemented on ARC/ARM and has been superseded
by irq_offload().
Some checks that were only done with CONFIG_LOAPIC_DEBUG fall
under the category of 'shouldn't ever happen' and have been
converted into assertions, instead of propagating return values
which are largely never checked.
Change-Id: I4eedca05bb7b384c4f3aa41a4f037f221f4a9cfe
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
This patch introduces the 'QMSI RTC device driver' which is simply a shim
driver based on RTC driver provided by QMSI BSP.
Some config options are independent of the driver implementation used,
so use a consistent name for them. In this case RTC Interrupt number and
Priority use the same config options for both the QMSI and DesignWare
drivers.
In order to enable this driver, the following options should be set:
CONFIG_QMSI_DRIVERS=y
CONFIG_QMSI_INSTALL_PATH="/path/to/libqmsi/directory"
CONFIG_RTC=y
CONFIG_RTC_QMSI=y
Change-Id: I48292406e5472e5786f3b9abbeb71016a273bfec
Signed-off-by: Andre Guedes <andre.guedes@intel.com>
Signed-off-by: Vinicius Costa Gomes <vinicius.gomes@intel.com>
If we are not doing any dynamic interrupts or exceptions, we
can put the IDT in ROM and save a considerable amount of RAM,
up to 2K if the IDT is the default size of 256 entries.
The _interrupt_vectors_allocated table can also be put in ROM
if we're not using any dynamic interrupts.
We introduce a new Kconfig option to force the IDT to be in RAM
for situations where no dynamic IRQs are used, but ROM footprint
needs to be conserved.
Change-Id: I38c9f1a8837b4db9f3dea1caa008374a26cbbf1d
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
This enables building with the iamcu variant of the x86 compiler
and enabled using the IAMCU ABIs.
Change-Id: Idf71251898e250b8df73c065462c93c289879fe2
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
There are a few bits missing on enabling I2C controller on
quark_d2000_crb. This adds the missing bits.
Change-Id: I05bbe8367a9e69962db573d496f1f9f0167ba597
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
This patch moves the CONFIG_STACK_CANARIES check from architecture's
Makefile to the root Makefile since this option is kernel-related,
not architecture-related. This way we avoid replicating the same
CONFIG_STACK_CANARIES check in several Makefiles.
This patch also removes some blank lines from the Makefiles it touches.
Change-Id: I458f92fa6799526c608369d1e56579936bcb196e
Signed-off-by: Andre Guedes <andre.guedes@intel.com>
Changes the nanokernel stack API so that the timeout parameter must be
specified when invoking nano_isr_stack_pop(), nano_fiber_stack_pop(),
nano_task_stack_pop() and nano_stack_pop().
This obsoletes the following APIs:
nano_fiber_stack_pop_wait()
nano_task_stack_pop_wait()
nano_stack_pop_wait()
Note that even though the new API requires that the timeout parameter
be specified, there are currently only two acceptable values:
TICKS_NONE and TICKS_UNLIMITED
This nanokernel option does not support CONFIG_NANO_TIMEOUTS.
Change-Id: Ic7f16ee30c3534115ceffa19ef8591ecc5a79080
Signed-off-by: Peter Mitsis <peter.mitsis@windriver.com>
Changes the nanokernel LIFO API so that the timeout parameter must be
specified when invoking nano_isr_lifo_get(), nano_fiber_lifo_get(),
nano_task_lifo_get() and nano_lifo_get().
This obsoletes the following APIs:
nano_fiber_lifo_get_wait()
nano_fiber_lifo_get_wait_timeout()
nano_task_lifo_get_wait()
nano_task_lifo_get_wait_timeout()
nano_lifo_get_wait()
nano_lifo_get_wait_timeout()
Change-Id: Ie9f93e46da42ea33c32544c02ab1d70b893cc198
Signed-off-by: Peter Mitsis <peter.mitsis@windriver.com>
Changes the nanokernel semaphore API so that the timeout parameter must be
specified when invoking nano_isr_sem_take(), nano_fiber_sem_take(),
nano_task_sem_take() and nano_sem_take().
This obsoletes the following APIs:
nano_fiber_sem_take_wait()
nano_fiber_sem_take_wait_timeout()
nano_task_sem_take_wait()
nano_task_sem_take_wait_timeout()
nano_sem_take_wait()
nano_sem_take_wait_timeout()
Change-Id: If7a4bce1bd8ec8d6410d04f3c16ff1922ff0910e
Signed-off-by: Peter Mitsis <peter.mitsis@windriver.com>
Changes the nanokernel FIFO API so that the timeout parameter must be
specified when invoking nano_isr_fifo_get(), nano_fiber_fifo_get(),
nano_task_fifo_get() and nano_fifo_get().
This obsoletes the following APIs:
nano_fiber_fifo_get_wait()
nano_fiber_fifo_get_wait_timeout()
nano_task_fifo_get_wait()
nano_task_fifo_get_wait_timeout()
nano_fifo_get_wait()
nano_fifo_get_wait_timeout()
Change-Id: Icbd2909292f1ced0bad8a70a075478536a141ef2
Signed-off-by: Peter Mitsis <peter.mitsis@windriver.com>
The UART on Quark SE and D2000 supports fractional clock divider.
It is used to limit frequency error for supported baud rates.
Change-Id: I1f39a95db09f4a5a4116edc700a10e4b9ecfa2bd
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Change terminology and use SoC instead of platform. An SoC provides
features and default configurations available with an SoC. A board
implements the SoC and adds more features and IP block specific to the
board to extend the SoC functionality such as sensors and debugging
features.
Change-Id: I15e8d78a6d4ecd5cfb3bc25ced9ba77e5ea1122f
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
This is a generic Atom configuration that can be inherited by boards
with Atom SoC like the minnowboard.
Change-Id: I06ab999062be7811d14755fd34440dee8f8b81ed
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
No need for the same SoC configuration with different names. Use IA32
as the "SoC" for qemu_x86 "boards".
Change-Id: Iee00538701c5ece14d0c3df637b0aaa54790f0e2
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Using LOAPIC Timer as default since it is the default for most target
X86 systems.
Change-Id: I71c9b307839ebcf46fb28e1b709089de600af83f
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
We had one pinmux per platform with support for multiple boards.
This moves pinmuxing to boards as first step. Common functions that
are exposed by the API need to be moved to driver while keeping the
muxing configuration with the boards.
Change-Id: I2b4fabf663db98d644abcb5d51ba83adc6f74541
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
The Galileo pinmux configuration and reboot code belong into
the board and not the SoC.
Change-Id: If862178569438a8901902088bd085275416c25ef
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Define boards based on platforms/SoCs and define them under boards/.
Also unify the naming of all platform, SoC and board files and use
platform.h for platforms and board.h for boards.
Change-Id: Icfeb96479ab5800aca98c80a79bdc3cecd645314
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
The Galileo board is based on the X1000 SoC, so move galileo to
boards and create this SoC instead, inheriting all SoC related code
and configuration items.
Change-Id: I9b39f1b44644775ee48acae284b82bae7876fffb
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
According to the schematic, SPI1_M_ should be properly mapped out
on the pinmux. This should enable the SPI1_M functionality on the
Arduino / Genuino 101 board now.
Change-Id: Ided0147e7c2d835aa58fdc5860e7ca7f55d9e566
Signed-off-by: Dan Kalowsky <daniel.kalowsky@intel.com>
Updating the pinmux to use a local static table for each pin select
option. Instead moving to a static series of function calls that
move the data from the RAM section to the ROM section.
This impacts only the Quark D2000 and the Quark SE chips. It does
not show any impact to the basic_minuteia tests.
All said we see small changes that amount to some values like:
test platform ram_%_change rom_%_change
======================== ============ ============ ============
microkernel:footprint-max quark_se-x86 -0.01 0.0
microkernel:footprint-reg quark_se-x86 -0.02 -0.01
microkernel:footprint-min quark_se-x86 -0.07 -0.02
nanokernel:footprint-max quark_se-x86 -0.02 -0.01
nanokernel:footprint-max quark_d2000 -0.01 -0.01
nanokernel:footprint-reg quark_se-x86 -0.03 -0.01
nanokernel:footprint-reg quark_d2000 -0.02 -0.02
nanokernel:footprint-min quark_se-x86 0.04 0.01
nanokernel:footprint-min quark_d2000 -0.07 -0.04
Change-Id: Ib69403eced60a8c784887dca9dd1954ce73a3e70
Signed-off-by: Dan Kalowsky <daniel.kalowsky@intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Currently the Quark SE and Quark D2000 platform are only included
through the use of a compile fence one level higher in the Makefile.
Adding in a secondary compile fence to ensure if that check ever
changes, we won't be in trouble.
Change-Id: I5e39faffb4289f80901c0264a50a3e770db3388a
Signed-off-by: Dan Kalowsky <daniel.kalowsky@intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Initial import of the pinmux configuration for the Quark_D2000 series
boards. Some minor tweaking of default values may be needed depending
upon expected usage scenarios.
Change-Id: I3b22219546a6534c7c695d0917a35f6f46b03cf1
Signed-off-by: Dan Kalowsky <daniel.kalowsky@intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Adding support for the pinmux pins to set the pullup and input enable
registers. On the Arduino_101 board some pullup pins specifically can
be used to cause a reset for the Arduino sketch being run. Its use on
other pins is currently being investigated.
Change-Id: Id3293a4da84ea5bf553bf62ccb12782cb88503a5
Signed-off-by: Dan Kalowsky <daniel.kalowsky@intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Naming convention should follow the IP_noun_verb concept. In this case,
renaming several functions from (for example) pinmux_set_pin to
pinmux_pin_set, while also correctly naming the function to their
specific tasks.
This is being done to make way for the ability to change the input
value, pullup value, and the slew as well.
Change-Id: Iec6f1723a48f80b66f3cea44df9bb6925972f6af
Signed-off-by: Dan Kalowsky <daniel.kalowsky@intel.com>
Extending the public interface of the pinmux to allow the end user
to set a pin as an input/output and to pull up the value on
a specified pin.
Change-Id: Ie0a3b6432dd8c7d7a02f32e3d22049bdd99f1410
Signed-off-by: Dan Kalowsky <daniel.kalowsky@intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Allow usage of alternative drivers and do not hardcode drivers
to zephyr own implementation.
Change-Id: Ieb55b5dc88b3643f276b7c48facef7f1c1c42fa7
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
The LCD display is an add-on, not a feature of the platform or the
board.
Set the defaults and remove the definition from Galileo Kconfig.
Change-Id: Ic319cd765d2dc1fe08cc65615680821fe9bc6a83
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
The pin mux for Galileo Gen2 isn't set properly to enable UART0_RXD input from
the Arduino headers. EXP1's pin0 OE_N needs to be set HIGH to make the IO0
buffer an Input.
Change-Id: I0167f11ff5ee87bd5afe17300807b1aa4ed17abf
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Signed-off-by: David Antler <david.a.antler@intel.com>
The argument to 'lidt' is a chunk of memory with the base address
and limit of the IDT, and not the IDT itself. Horrible things
were happening when the IDT itself was being passed to this
instruction.
To be extra safe, disable interrupts while we modify the table
and subsequently reload it.
Change-Id: I9bf96f13a5f6e1be80d11bbfb9db3df1f2ed613a
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Add support for compilers conforming to the IAMCU calling convention
as documented by
https://github.com/hjl-tools/x86-psABI/wiki/iamcu-psABI-0.7.pdf
Change-Id: I6fd9d5bede0538b2049772e3850a5940c5dd911e
Signed-off-by: Dirk Brandewie <dirk.j.brandewie@intel.com>
All of these stubs at the end pop the stack and tell the LOAPIC
that we are at EOI. Put this in common code which falls through to
_IntExit(). Saves 8 bytes per static IRQ stub. There is also small
constant savings in the common code for dynamic IRQs.
Change-Id: If17e9f105928a4251a2cb3fc0d192649c1c4d84b
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Quark SE Lakemont core has a hardware bug where the LOAPIC does
not properly notify the IOAPIC to clear the IRR bit for level-
triggered interrupts.
This patch introduces a workaround where the vector ID of the
in-service interrupt is manually written to the IOAPIC_EOI
register, resulting in the bit being cleared.
Unfortunately, in the context where EOI happens it's very difficult
to identify which IRQ line is being serviced, so this is done
unconditionally for all interrupts vectors whether they are registered
in the IOAPIC RTE table or not.
Change-Id: I639cd258dec4f50934e17eadbb821e6a7112e636
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Instead of having two config options to specify interrupt triggering
conditions, merge them into one option and clarify. This is now
similar to other drivers which have interrupt triggers.
Change-Id: I4e60c8c45a08d005dcc8256cb89e4c5be7c94307
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Move the common #define for IOAPIC interrupt trigger flags out of
platform board.h and into the driver.
Change-Id: I89090181acb5f48dd797e7773ab65c5f3d46c42a
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Move the common #define for IOAPIC interrupt trigger flags out of
platform board.h and into the driver.
Change-Id: Ie7262b69226ebffa7e1b9e35725fda24b3fe089f
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Move the common #define for IOAPIC interrupt trigger flags out of
platform board.h and into the driver.
Change-Id: I2d50457a45fae62ff085f7239712d580243253bb
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Move the common #define for IOAPIC interrupt trigger flags out of
platform board.h and into the driver.
Change-Id: Ia0a069464392714f38037841de52e8d265fa4f49
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
The APIC by default uses vector 0xFF for the spurious interrupt
vector as described in the x86 CPU manual volume 3 section 10.9.
Make this its own config option defaulting to 32.
MVIC doesn't have a spurious interrupt vector, and due to the
fixed IRQ-to-vector mapping for this controller, continue
to use the last available entry.
Change-Id: I29bd09df700629dc0d15b30a6ae590b0df1ef890
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
This was only needed for an older implementation of software interrupts,
now superseded by the irq_offload() API (which doesn't interact with
the interrupt controller at all)
Change-Id: I8aa696d370ae1799872f6d70de69f3cb5b47456a
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
To many people, IPI connotes inter-processor interrupts on SMP
systems. Rename this to IPM, or Inter-Processor Mailboxes.
Change-Id: I032815e23c69a8297c0a43992132441c240fb71e
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
define CONFIG_PLATFORM only once in arch/Kconfig and set it
for every platform.
Change-Id: I8554bb36d2d15c3ee71fa63dfc3a763ebca956ee
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
excecptions are handled the same for i386_sysV_abi and iamcu calling
conventions ATM since we do not have any exceptions that we can
recover from there is no reason to have seperate implementations.
Change-Id: Ica8b332d7756a91b56f7080ac74771ad25d32753
Signed-off-by: Dirk Brandewie <dirk.j.brandewie@intel.com>
Add null definitions for the interrupt latency measurement API so we
can remove compile fences in C code.
Change-Id: If86eedf79afcb49002108814dd4fb864956eb667
Signed-off-by: Dirk Brandewie <dirk.j.brandewie@intel.com>
functions defined in header files needs to be 'static inline' to
avoid linker issues if they are used more than once.
Change-Id: I2feb3560bde7cbc9a5c7932eca585be8036f3b25
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Other internal functions are shown in this header, no reason to
keep this a secret.
Change-Id: Icb7d36206148c281f1960d1ac10368d9bb3033f1
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
According to the datasheet, there is some caching going on as a
performance optimization and the IDT needs to be re-loaded if any
changes are made at runtime.
Change-Id: I23864e1109907512066a9f8f3a36e3f719b9174b
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
The initialization code and macros are the same. So extracts it
and puts it into the driver. This is another step to follow
the driver model.
Those empty C files are there because the current Kbuild
requires Makefile to be present at those directories,
(due to arch/x86/Kbuild), which requires building some object
files. So the empty source files are there to produce empty
object files to satisfy this.
Change-Id: I14056347ea14cff227d9e8960192e8673c0019b8
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
The initialization code and macros are the same. So extracts it
and puts it into the driver. This is another step to follow
the driver model.
Change-Id: I1d379068f64855d5d4595838040ec50f97f638a0
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
The initialization code and macros are the same. So extracts it
and puts it into the driver. This is another step to follow
the driver model.
Change-Id: I1af8b2888779b2b58367feaff9ee1a6d97b4873c
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
() Fix compilation errors due to variable ordering.
() Fix the default config for Quark/SE SS as
the kconfig options were renamed in previous
patches.
Change-Id: I1004ae332fb857b60ed90df59831e7bd9c490cb8
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Saves an errno per-thread, retrieved via _get_errno(), instead of
changing the value of a global variable during context switches to avoid
a hit to the context switch performance.
Per-arch asm implementations are provided for maximum performance.
Enabled by default, but can be disabled via the CONFIG_ERRNO option.
Change-Id: I81d57a2e318c94c68eee913ae0d4ca3a3609c7a4
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
() The SCSS has some additional registers to mask interrupts
from peripherals. This patch unmasks the interrupts for
the two UARTs on board, so that interrupts can be delivered.
() The UART interrupts are edge-triggerd, so set the config
options accordingly.
Change-Id: I39a1edccd830a8a19288982efa2e9d0faaaff8ba
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Clock gating is platform specific and not mandatory. Thus making it
Kconfig based as well as generic.
Change-Id: I4ea10eadb077ac3d57c9337b43b1a9fb14763302
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
Clock gating is platform specific and not mandatory. Thus making in
Kconfig based as well as generic.
Change-Id: I01b7831536efd87cc66a95060fcf1faf4a340073
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
Let's apply the interruption unmasking if only the mask is defined.
Which definition should be done in board.h thus applying the change to
quark_se and quark_d2000 platforms
Change-Id: I9c273e2e7e33dd077a54e8f9205fa949a5e3707a
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
Let's apply the interruption unmasking if only the mask is defined.
Which definition should be done in board.h thus applying the change to
quark_se and quark_d2000 platforms
Change-Id: Ie0a4912f0dfbd97f2273efed963f7810a985c0bd
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
Base address, IRQ, interrupt priority as well as the instance name: all
are now Kconfig based. Thus Applying the change to quark_se and
quark_d2000 platforms. Sample code is updated as well.
Change-Id: I1c225c1b68d94b22ca10423b50a78a0ba09a27a5
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
Base address, IRQ, interrupt priority as well as the instance name: all
are now Kconfig based. Thus Applying the change to quark_se and
quark_d2000 platforms. Sample code is updated as well.
Change-Id: Idcc89e6e9f4acc337fafc7d42f8de3061a5ece04
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
Removed old style file description and documnetation and apply
doxygen synatx.
Change-Id: I3ac9f06d4f574bf3c79c6f6044cec3a7e2f6e4c8
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
This patch remove the dependency of the ADVANCE_POWER_MANAGEMENT
for profiling sleep events that was supported only for microkernel.
Allowing us to also use this feature in nanokernel-only systems.
Change-Id: I1761eb6c4d72f477b419dfca5dc152b0fb69ee27
Signed-off-by: Yonattan Louise <yonattan.a.louise.mendoza@intel.com>
Set correct interrupt flags which are used with the console
handler.
Change-Id: I6a3a76826cedd0b4116f622701f2cb1161dd8adc
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Set correct interrupt flags which are used with the console
handler.
Change-Id: I473a1fca6234ffb8d926457e8ccecfa29d1be6a5
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Set correct interrupt values for this platform.
Change-Id: I97361b4420630e73bb8c8f812c943ee972cb8762
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Removes the 'priority' parameter from the IRQ_CONFIG macro.
This parameter was not used anymore in any architecture.
The priority is handled in the IRQ_CONNECT macro.
The documentation is updated as well.
Change-Id: I24a293c5e41bd729d5e759113e0c4a8a6a61e0dd
Signed-off-by: Juan Manuel Cruz <juan.m.cruz.alcaraz@linux.intel.com>
Although it contains functions called from ASM-land, there's no
calling-convention specific code here.
Change-Id: I3d912bdf28e6f3e797e6a2d6b745302b4c884b4a
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
The content of include/drivers/hpet.h is really private to
the driver and does not need to be exposed in public include
directory. So move the content into driver code.
Change-Id: Ica442e43c480a6b079b8d3c4e75e67adcfd0ba6b
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Setting up new platforms to handle emulation, and make them the only
ones able to run on QEMU from the Makefile "qemu" target to avoid
confusion with other platforms. We have now platform qemu_x86 and
platform qemu_cortex_m3, also modification to the sanity checks to have
qemu support only on those platforms
Signed-off-by: Sergio Rodriguez <sergio.sf.rodriguez@intel.com>
Change-Id: I9291918a1d58fea4f37750ada78234628f9a5d98
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Since all the necessary bits utilizing UART by index have moved to
use device name instead, the uart_devs[] can finally be removed.
Change-Id: Idbae6b46c0af9eef6c22c59e121e9d6a6b52426a
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Use device name to find the UART device for uart_pipe usage,
instead of relying on an arbitrary index.
Change-Id: I36aaa4ed8f0b4905e4e741ca1464947e59f30869
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Use device name to find the UART device for Bluetooth usage,
instead of relying on an arbitrary index.
The default device names being used are derived from the original
board.h for each platform. Some of them point to the same device
as UART console. Since this is a Kconfig option, the default
can be overridden so this is not a serious issue.
Change-Id: Ibe82f3968e72ba60f9c033aa3dfcb2fb3c41dc75
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Use device name to find the UART device for console usage, instead of
relying on an arbitrary index.
Change-Id: Iebe01c9bf392dfee6d8284367f67647f7d47561a
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Remove the call to uart_init(), and let the UART drivers take care of
the port initialization.
Change-Id: Id3e46135ab993cb6596b1fb5339ab1664c65ab40
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Remove the call to uart_init(), and let the UART drivers take care of
the port initialization.
Change-Id: Ibeca65b3fe64feb7a203a793c01c525ff5e6afda
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
() Renames ns16550.c to uart_ns16550.c. This is to follow
the driver naming convention.
() Renames functions ns16550_uart_*() to uart_ns16550_*(),
following driver naming convention.
() UART ports initialization is moved into the driver itself.
All the init code in platform config files is removed.
() Adds (many) Kconfig options. These don't have to be defined
in each platform's board.h anymore.
() Renames CONFIG_NS16550_* to CONFIG_UART_NS16550_*
() Disable NS16550 for ARC as no port is defined anyway.
Change-Id: I76bbe25b9bc75eb62df81e533f84f4f63a5257b7
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
The IRQ line used for MVIC timer interrupts is 0, not 10.
Change-Id: I076bf9c8902e7384e493945e6689fcbefff59cad
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
This is currently valid for quark_se platform. It's used internally to
suspend and/or resume the gpio controller.
Change-Id: I5147568ba6b0450363566b5f9fd2e8aa7e41df49
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
Change-Id: Ie58e8611a8fe9edec9ebcb123532a97f396098f4
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
There is no secondary GPIO controller on such SoC. Plus, the unique
controller controls at least 28 pins (if not 32, so I set 32), as
verified on boards.
Change-Id: I61c563671a908551250faa2a0fb9f9e2e17018d3
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
Simplify driver by using sys_io functions and implement
wdt_read_config
Change-Id: I119615f1c391daae43a3b8db30319c51167ae05b
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Software interrupts or system calls aren't really appropriate for
zephyr, but we have an ongoing need in our test code to run a
function with arguments synchronously in interrupt context.
This patch introduces irq_offload() which allows us to do this without
separate initialization or having to manage fake IRQs in the
interrupt controller.
ARM assembly code contributed by Benjamin Walsh
<benjamin.walsh@windriver.com>
ARC is not yet implemented but will be in a subsequent patch.
irq_test_common.h has been removed and all test cases updated to
use the new API.
Change-Id: I9af99ed31b62bc7eb340e32cf65e3d11354d1ec7
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Put initialization priorities as device driver Kconfig
parameter.
Initialization priority value for each platform is defined
in the platform Kconfig file.
Drivers and platform code use SYS_DEFINE_DEVICE to add
and initialization function.
Change-Id: I2f4f3c7370dac02408a1b50a0a1bade8b427a282
Signed-off-by: Dmitriy Korovkin <dmitriy.korovkin@windriver.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Avoid having to remove quotes wherever the platform name is used
by exporting the variable only once.
Change-Id: I4cb51901e4ac19d70d0310fe6bbacd157f586661
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Add comment regarding the use of GAS when using clang, and remove
duplication of setting -Wa,--divide, which is needed for all toolchains.
Change-Id: Iab7257b038d1f4142c37a6c6c5979ef28f78a655
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
Move the files that *know* about the calling convention in use by the
compiler. The routines exposed by the files moved to the i386_sysV_abi
directory follow the C calling convention specified by the
i386_sysV_abi which is the default for GCC. The upstream GCC has been
enhanced to support the iamcu_ABI that is optimized for processors
that implement the IA MCU instruction set. This new ABI provides code,
data and stack size improvements on IA MCU based systems.
This change is the first step in adding support for the IA MCU
optimized toolchains to Zephyr OS
Change-Id: I13bffee8007fb3f82aa31389b2c241065e8e315d
Original-work-by: Dirk Brandewie <dirk.j.brandewie@intel.com>
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
When building for a certain platform, we have no idea
what architecture we are building for.
We used to specify the architecture alongside the board or platform
name and this was used to find the defconfig in arch/<arch>/configs.
By putting all board configurations we support in one place we do
not have to specify the architecture, just the configuration name.
Change-Id: Ib7e9f63b9a8051714dc207f583fd26ef620497d8
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Do not depend on host architecture and use architecture definition
from the defconfig file of the board.
Change-Id: Idb3dd42524f26bd167a34d6eb024d4d9816e9730
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Do not depend on environment variables and use a kconfig variable
for defining the architecture.
In addition, remove the X86_32 variable, it just duplicates X86 for
not good reason, at least until start supporting MCUs with 64bit.
Change-Id: Ia001db81ed007e6a43f34506fed9be1345b88a4b
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Do not reference every platform, instead use the platform
name to tell make what to build.
Change-Id: I7498da7cdcdada754466222902f59fe4c6487d89
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Move platform related data and definition to the platform
directory and include it using:
arch/<arch>/platforms/*/Kconfig.platform
This way we will able to add a platform as a directory of
content without the need to change and Kconfig files.
Platforms can then be included by reference (using repo or
git submodules and does not need to be part of the zephyr
project)
Change-Id: I5e71f5394c22edb346f7d61d9448b8e1c68e1f9b
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Provide the proper irq for i2c, gpio and spi. And make relevant drivers
getting enabled easily once their domain is selected.
Change-Id: Ib8a428e11b6163a1b370b23baa34ea2fab733565
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
Without that, it won't built when enabling support for dw i2c in
quark_se-x86.
Change-Id: Icce26488d870c273516dc9f34555176122bcb9c8
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
- Build the actual driver when relevant
- Provide the IOAPIC stub
- Provide the IRQ flags for IRQ_CONNECT_STATIC
- Set the default IRQ priorities
Change-Id: Iea20ef67c92cf7f48791fba5a8021448b7059950
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
Original name was too generic and confusing. This patch renames
driver to pipe UART and moves it to console drivers folder. Kconfig
destription is also improved.
Change-Id: I716fdbf7d636bbdc03b0fce27a59fd866f473246
Signed-off-by: Szymon Janc <ext.szymon.janc@tieto.com>
The Intel Quark microcontroller D2000, is a low power, battery-operated,
32-bit microcontroller. Within its small footprint, the Intel Quark
microcontroller D2000 includes an Intel Quark ultra-low-power core
running at 32 MHz, with 32k integrated flash and 8k OTP SRAM.
Change-Id: I6ba121996edb0b5fbe596bd6ef3d6e3979ff73e9
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
