Commit graph

1037 commits

Author SHA1 Message Date
Johann Fischer 08df5961b3 arch: intel_quark: use DW device driver when USB is selected
This patch allows more generic USB configuration in the samples
and removes platform dependent driver configuration.

Signed-off-by: Johann Fischer <j.fischer@phytec.de>
2017-06-28 15:14:15 -04:00
Savinay Dharmappa ce1add260b dts: x86: Add dts support for x86
patch adds necessary files and does the modification to the existing
files to add device support for x86 based intel quark microcontroller

Signed-off-by: Savinay Dharmappa <savinay.dharmappa@intel.com>
2017-06-22 10:23:39 -05:00
Anas Nashif 397d29db42 linker: move all linker headers to include/linker
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2017-06-18 09:24:04 -05:00
Adithya Baglody be1cb961ad tests: benchmark: boot_time: Reading time stamps made arch agnostic
1. Changed _tsc_read() to k_cycles_get_32(). Thus reading the
time stamp will be agnostic of the architecutre used.
2. Changed the variable names from *_tsc to *_time_stamp.

JIRA: ZEP-1426

Signed-off-by: Adithya Baglody <adithya.nagaraj.baglody@intel.com>
2017-06-16 07:37:37 -05:00
Adithya Baglody 05c9dd08b0 quark_se: MMU: Add linker support for MMU page table generation.
Add a separate section in the linker to place the MMU configuration
information. This location is read by the gen_mmu.py script to
create the actual page tables.

JIRA: ZEP-2095

Signed-off-by: Adithya Baglody <adithya.nagaraj.baglody@intel.com>
2017-06-13 11:36:54 -04:00
Adithya Baglody aab1c1f63c quark_se: MMU: Memory regions for arduino 101(quark_se)
Define the memory regions needed to generate boot time page tables.

JIRA: ZEP-2097

Signed-off-by: Adithya Baglody <adithya.nagaraj.baglody@intel.com>
2017-06-13 11:36:54 -04:00
Adithya Baglody 43dfd98469 kernel: x86: MMU: Enable MMU at boot time.
In crt0.S the MMU is initialized. It uses the statically build
page tables. Here 32-bit paging scheme is used, thereby each page
table entry maps to a 4KB page. The valid regions of the memory are
specified by SOC specific file(soc.c).

JIRA: ZEP-2099

Signed-off-by: Adithya Baglody <adithya.nagaraj.baglody@intel.com>
2017-06-13 11:36:54 -04:00
Adithya Baglody 576c1ebba2 qemu: MMU: Memory regions for qemu_x86
Define the memory regions needed to generate boot time page
tables.

JIRA:ZEP-2098

Signed-off-by: Adithya Baglody <adithya.nagaraj.baglody@intel.com>
2017-06-13 11:36:54 -04:00
Adithya Baglody 83644a493e kernel: x86: MMU: Build system support for x86 MMU
Makefile rule to create the MMU page tables at boot time. This
rule invokes the gen_mmu.py script to create a binary which is
then placed into the kernel image using objcopy.
Makefile.mmu is included only when CONFIG_X86_MMU is enabled.

JIRA: ZEP-2095

Signed-off-by: Adithya Baglody <adithya.nagaraj.baglody@intel.com>
2017-06-13 11:36:54 -04:00
Adithya Baglody 9bbf5335b9 kernel: x86: MMU: Macros & Linker scripts for Boot time table creation
Macro is used to create a structure to specify the boot time
page table configuration. Needed by the gen_mmu.py script to generate
the actual page tables.

Linker script is needed for the following:
     1. To place the MMU page tables at 4KByte boundary.
     2. To keep the configuration structure created by
        the Macro(mentioned above).

Signed-off-by: Adithya Baglody <adithya.nagaraj.baglody@intel.com>
2017-06-13 11:36:54 -04:00
Adithya Baglody 569c6e5203 kernel: MMU: kconfig definition to enable the MMU on x86.
Kconfig definition for enabling the memory management Unit
on x86 based platforms.

JIRA: ZEP-2093

Signed-off-by: Adithya Baglody <adithya.nagaraj.baglody@intel.com>
2017-06-13 11:36:54 -04:00
Anas Nashif 243671bcdb samples: ipm: fix macro name
replace undefined K_STACK_DECLARE with K_THREAD_STACK_DEFINE.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2017-06-09 22:36:23 -04:00
Andrew Boie 567c6c7683 misc: use K_THREAD_STACK_DEFINE macros
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2017-06-09 18:53:28 -04:00
Andrew Boie e3550a29ff stack_sentinel: hang system on failure
Stack sentinel doesn't prevent corruption, it just notices when
it happens. Any memory could be in a bad state and it's more
appropriate to take the entire system down rather than just kill
the thread.

Fatal testcase will still work since it installs its own
_SysFatalErrorHandler.

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2017-06-08 13:49:36 -05:00
Andrew Boie 998f905445 arches: declare _SysFatalErrorHandler __weak
This function is intended to be easily overridable by applications.

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2017-06-08 13:49:36 -05:00
Andrew Boie ae1a75b82e stack_sentinel: change cooperative check
One of the stack sentinel policies was to check the sentinel
any time a cooperative context switch is done (i.e, _Swap is
called).

This was done by adding a hook to _check_stack_sentinel in
every arch's __swap function.

This way is cleaner as we just have the hook in one inline
function rather than implemented in several different assembly
dialects.

The check upon interrupt is now made unconditionally rather
than checking if we are calling __swap, since the check now
is only called on cooperative _Swap(). The interrupt is always
serviced first.

Issue: ZEP-2244
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2017-06-08 13:49:36 -05:00
Andrew Boie 3989de7e3b kernel: fix short time-slice reset
The kernel tracks time slice usage with the _time_slice_elapsed global.
Every time the timer interrupt goes off and the timer driver calls
_nano_sys_clock_tick_announce() with the elapsed time, this is added to
_time_slice_elapsed. If it exceeds the total time slice, the thread is
moved to the back of the queue for that priority level and
_time_slice_elapsed is reset to zero.

In a non-tickless kernel, this is the only time _time_slice_elapsed is
reset.  If a thread uses up a partial time slice, and then cooperatively
switches to another thread, the next thread will inherit the remaining
time slice, causing it not to be able to run as long as it ought to.

There does exist code to properly reset the elapsed count, but it was
only compiled in a tickless kernel. Now it is built any time
CONFIG_TIMESLICING is enabled.

Issue: ZEP-2107
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2017-06-02 14:47:01 -04:00
Anas Nashif b330e0e4a9 Revert "x86: call gen_idt with $ZEPHYR_BASE too"
This reverts commit 37f4178f58.

This change builds gen_idt in the zephyr project tree instead of
building it in outdir of the application. The build process should all
happen inside outdir and no binaries should be placed in the zephyr
tree.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2017-06-01 10:26:57 -04:00
Johan Hedberg 9516d63836 Bluetooth: Remove support for NBLE
NBLE has been deprecated for a few releases now and can be removed.

Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
2017-05-25 09:03:16 -07:00
Tomasz Bursztyka 62941365b0 arch/x86/quark_se: Let the possibility to use native SPI driver
Set the right definitions to be able to use SPI_DW instead of SPI_QMSI.

Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
2017-05-19 18:52:25 -04:00
Andrew Boie 5dcb279df8 debug: add stack sentinel feature
This places a sentinel value at the lowest 4 bytes of a stack
memory region and checks it at various intervals, including when
servicing interrupts or context switching.

This is implemented on all arches except ARC, which supports stack
bounds checking directly in hardware.

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2017-05-13 15:14:41 -04:00
Andrew Boie 174f301147 build: simplfy how extra build steps are specified
For various reasons its often necessary to generate certain
complex data structures at build-time by separate tools outside
of the C compiler. Data is populated to these tools by way of
special binary sections not intended to be included in the final
binary. We currently do this to generate interrupt tables, forthcoming
work will also use this to generate MMU page tables.

The way we have been doing this is to generatea "kernel_prebuilt.elf",
extract the metadata sections with objcopy, run the tool, and then
re-link the kernel with the extra data *and* use objcopy to pull
out the unwanted sections.

This doesn't scale well if multiple post-build steps are needed.
Now this is much simpler; in any Makefile, a special
GENERATED_KERNEL_OBJECT_FILES variable may be appended to containing
the filenames to the generated object files, which will be generated
by Make in the usual fashion.

Instead of using objcopy to pull out, we now create a linker-pass2.cmd
which additionally defines LINKER_PASS2. The source linker script
can #ifdef around this to use the special /DISCARD/ section target
to not include metadata sections in the final binary.

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2017-05-13 14:07:09 -04:00
Andrew Boie 3d3d6a85df x86: remove hacks to include functions
None of this is currently necessary, the spurious interrupt
stubs and exception entry code is included in the binary just
fine. To make matters worse, some data referenced lives in the
.intList section which is completely stripped out of the binary.

If in the future we find certain essential functions are being
garbage collected when they should not be, the proper way to
mitigate this is with KEEP() directives in the linker script.

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2017-05-13 14:07:09 -04:00
Andrew Boie d26cf2dc33 kernel: add k_thread_create() API
Unline k_thread_spawn(), the struct k_thread can live anywhere and not
in the thread's stack region. This will be useful for memory protection
scenarios where private kernel structures for a thread are not
accessible by that thread, or we want to allow the thread to use all the
stack space we gave it.

This requires a change to the internal _new_thread() API as we need to
provide a separate pointer for the k_thread.

By default, we still create internal threads with the k_thread in stack
memory. Forthcoming patches will change this, but we first need to make
it easier to define k_thread memory of variable size depending on
whether we need to store coprocessor state or not.

Change-Id: I533bbcf317833ba67a771b356b6bbc6596bf60f5
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2017-05-11 20:24:22 -04:00
Adithya Baglody d03b2496cd test: benchmarking: Timing metrics for the kernel
JIRA: ZEP-1822, ZEP-1823, ZEP-1825

Signed-off-by: Adithya Baglody <adithya.nagaraj.baglody@intel.com>
2017-05-03 08:46:30 -04:00
Andrew Boie 8bfee13cd3 x86: define MMU data structures
This was more or less transplanted from old Viper codebase (Zephyr's
ancestor which supported paging) and adapted to current coding style.

Change-Id: I203e631f1dcd5f2fb4e9a2fa9339fc7521c7962d
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2017-04-27 17:46:54 +00:00
Ramesh Thomas 89ffd44dfb kernel: tickless: Add tickless kernel support
Adds event based scheduling logic to the kernel. Updates
management of timeouts, timers, idling etc. based on
time tracked at events rather than periodic ticks. Provides
interfaces for timers to announce and get next timer expiry
based on kernel scheduling decisions involving time slicing
of threads, timeouts and idling. Uses wall time units instead
of ticks in all scheduling activities.

The implementation involves changes in the following areas

1. Management of time in wall units like ms/us instead of ticks
The existing implementation already had an option to configure
number of ticks in a second. The new implementation builds on
top of that feature and provides option to set the size of the
scheduling granurality to mili seconds or micro seconds. This
allows most of the current implementation to be reused. Due to
this re-use and co-existence with tick based kernel, the names
of variables may contain the word "tick". However, in the
tickless kernel implementation, it represents the currently
configured time unit, which would be be mili seconds or
micro seconds. The APIs that take time as a parameter are not
impacted and they continue to pass time in mili seconds.

2. Timers would not be programmed in periodic mode
generating ticks. Instead they would be programmed in one
shot mode to generate events at the time the kernel scheduler
needs to gain control for its scheduling activities like
timers, timeouts, time slicing, idling etc.

3. The scheduler provides interfaces that the timer drivers
use to announce elapsed time and get the next time the scheduler
needs a timer event. It is possible that the scheduler may not
need another timer event, in which case the system would wait
for a non-timer event to wake it up if it is idling.

4. New APIs are defined to be implemented by timer drivers. Also
they need to handler timer events differently. These changes
have been done in the HPET timer driver. In future other timers
that support tickles kernel should implement these APIs as well.
These APIs are to re-program the timer, update and announce
elapsed time.

5. Philosopher and timer_api applications have been enabled to
test tickless kernel. Separate configuration files are created
which define the necessary CONFIG flags. Run these apps using
following command
make pristine && make BOARD=qemu_x86 CONF_FILE=prj_tickless.conf qemu

Jira: ZEP-339 ZEP-1946 ZEP-948
Change-Id: I7d950c31bf1ff929a9066fad42c2f0559a2e5983
Signed-off-by: Ramesh Thomas <ramesh.thomas@intel.com>
2017-04-27 13:46:28 +00:00
Ramesh Thomas 62eea121b3 kernel: tickless: Rename _Swap to allow creation of macro
Future tickless kernel patches would be inserting some
code before call to Swap. To enable this it will create
a mcro named as the current _Swap which would call first
the tickless kernel code and then call the real __swap()

Jira: ZEP-339
Change-Id: Id778bfcee4f88982c958fcf22d7f04deb4bd572f
Signed-off-by: Ramesh Thomas <ramesh.thomas@intel.com>
2017-04-27 13:46:26 +00:00
Andrew Boie 73abd32a7d kernel: expose struct k_thread implementation
Historically, space for struct k_thread was always carved out of the
thread's stack region. However, we want more control on where this data
will reside; in memory protection scenarios the stack may only be used
for actual stack data and nothing else.

On some platforms (particularly ARM), including kernel_arch_data.h from
the toplevel kernel.h exposes intractable circular dependency issues.
We create a new per-arch header "kernel_arch_thread.h" with very limited
scope; it only defines the three data structures necessary to instantiate
the arch-specific bits of a struct k_thread.

Change-Id: I3a55b4ed4270512e58cf671f327bb033ad7f4a4f
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2017-04-26 16:29:06 +00:00
Inaky Perez-Gonzalez 37f4178f58 x86: call gen_idt with $ZEPHYR_BASE too
When calling scripts/gen_idt, if we don't have $ZEPHYR_BASE/scripts in
the path, it will fail, so we can call it with its full path to avoid
such need.

Change-Id: I47b340c9f3204ad8740c29e663e12082208bb13b
Signed-off-by: Inaky Perez-Gonzalez <inaky.perez-gonzalez@intel.com>
2017-04-25 02:32:29 +00:00
Kumar Gala 4f1e304f68 build: only build gen_idt on x86
Change-Id: I0401e2557c69f1e32ddedb79758c1dde781ea69b
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2017-04-24 03:17:16 +00:00
Andrew Boie 7827b7bf4a x86: exception-assisted panic/oops support
We reserve a specific vector in the IDT to trigger when we want to
enter a fatal exception state from software.

Disabled for drivers/build_all tests as we were up to the ROM limit
on Quark D2000.

Issue: ZEP-843
Change-Id: I4de7f025fba0691d07bcc3b3f0925973834496a0
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2017-04-22 10:31:49 -04:00
Andrew Boie cdb94d6425 kernel: add k_panic() and k_oops() APIs
Unlike assertions, these APIs are active at all times. The kernel will
treat these errors in the same way as fatal CPU exceptions. Ultimately,
the policy of what to do with these errors is implemented in
_SysFatalErrorHandler.

If the archtecture supports it, a real CPU exception can be triggered
which will provide a complete register dump and PC value when the
problem occurs. This will provide more helpful information than a fake
exception stack frame (_default_esf) passed to the arch-specific exception
handling code.

Issue: ZEP-843
Change-Id: I8f136905c05bb84772e1c5ed53b8e920d24eb6fd
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2017-04-22 10:31:49 -04:00
Kumar Gala 96ee45df8d kernel: refactor thread_monitor_init into common code
We do the same thing on all arch's right now for thread_monitor_init so
lets put it in a common place.  This also should fix an issue on xtensa
when thread monitor can be enabled (reference to _nanokernel.threads).

Change-Id: If2f26c1578aa1f18565a530de4880ae7bd5a0da2
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2017-04-21 20:34:42 +00:00
Kumar Gala b8823c4efd kernel: Refactor common _new_thread init code
We do a bit of the same stuff on all the arch's to setup a new thread.
So lets put that code in a common place so we unify it for everyone and
reduce some duplicated code.

Change-Id: Ic04121bfd6846aece16aa7ffd4382bdcdb6136e3
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2017-04-21 20:34:42 +00:00
Kumar Gala 5742a508a2 kernel: cleanup use of naked unsigned in _new_thread
There are a few places that we used an naked unsigned type, lets be
explicit and make it 'unsigned int'.

Change-Id: I33fcbdec4a6a1c0b1a2defb9a5844d282d02d80e
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2017-04-21 20:34:41 +00:00
Kumar Gala cc334c7273 Convert remaining code to using newly introduced integer sized types
Convert code to use u{8,16,32,64}_t and s{8,16,32,64}_t instead of C99
integer types.  This handles the remaining includes and kernel, plus
touching up various points that we skipped because of include
dependancies.  We also convert the PRI printf formatters in the arch
code over to normal formatters.

Jira: ZEP-2051

Change-Id: Iecbb12601a3ee4ea936fd7ddea37788a645b08b0
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2017-04-21 11:38:23 -05:00
David B. Kinder 36bb36475f spell: fix Kconfig help typos: /arch
Fix misspellings in Kconfig help text

Change-Id: I2a753b57107f09073eb84ac757ac1e180ae89349
Signed-off-by: David B. Kinder <david.b.kinder@intel.com>
2017-04-21 12:30:42 +00:00
Kumar Gala bf53ebf2c8 arch: convert to using newly introduced integer sized types
Convert code to use u{8,16,32,64}_t and s{8,16,32,64}_t instead of C99
integer types.  There are few places we dont convert over to the new
types because of compatiability with ext/HALs or for ease of transition
at this point.  Fixup a few of the PRI formatters so we build with newlib.

Jira: ZEP-2051

Change-Id: I7d2d3697cad04f20aaa8f6e77228f502cd9c8286
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2017-04-21 12:08:12 +00:00
Kumar Gala 789081673f Introduce new sized integer typedefs
This is a start to move away from the C99 {u}int{8,16,32,64}_t types to
Zephyr defined u{8,16,32,64}_t and s{8,16,32,64}_t.  This allows Zephyr
to define the sized types in a consistent manor across all the
architectures we support and not conflict with what various compilers
and libc might do with regards to the C99 types.

We introduce <zephyr/types.h> as part of this and have it include
<stdint.h> for now until we transition all the code away from the C99
types.

We go with u{8,16,32,64}_t and s{8,16,32,64}_t as there are some
existing variables defined u8 & u16 as well as to be consistent with
Zephyr naming conventions.

Jira: ZEP-2051

Change-Id: I451fed0623b029d65866622e478225dfab2c0ca8
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2017-04-20 16:07:08 +00:00
Anas Nashif 8df439b40b kernel: rename nanoArchInit->kernel_arch_init
Change-Id: I094665e583f506cc71185cb6b8630046b2d4b2f8
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2017-04-19 10:59:35 -05:00
Kumar Gala fded58d2af Revert "arch: Convert formatter strings to use PRI defines"
This reverts commit da8bff6b20.

We revert this as we intent to move away from {u}int{8,16,32,64}_t types
to our own internal types for sized variables so we shouldn't need the
PRI macros anymore.

Change-Id: Ibb1fae7500bddb4772b8830d497a0e5f78b44bcc
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2017-04-19 10:50:51 -05:00
Kumar Gala da8bff6b20 arch: Convert formatter strings to use PRI defines
To allow for various libc implementations (like newlib) in which the way
various {u}int{8,16,32}_t types are defined vary between both libc
implementations and across architectures we need to utilize the PRI
defines.

Change-Id: Ic4e65db52c8d693228cf80584283d4d06e68b5ad
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2017-04-17 11:09:36 -05:00
Piotr Mienkowski a8de9ff438 drivers: i2c: rename IRQ SHARED/DIRECT Kconfig options
I2C_SHARED_IRQ, I2C_0_IRQ_SHARED, I2C_0_IRQ_DIRECT Kconfig options
are DW driver specific. Its presence is confusing for a user of any
other I2C driver than DW. This patch renames these options to include
DW string and makes it visible only for DW I2C driver. This is a
similar implementation to that used by ETH DW Ethernet driver.

Change-Id: I795506f9b103c028a22317df9ad632dce5cd1343
Signed-off-by: Piotr Mienkowski <piotr.mienkowski@gmail.com>
2017-04-14 01:58:33 +00:00
Luiz Augusto von Dentz 0dc022f7fa x86: Increase RAM_SIZE to 256K
When running with qemu often times the developer want to enable all
sorts of debugs which end up not working with only 192K.

Change-Id: I8d784618b9a0d911944f831a4058b34abc0c3e35
Signed-off-by: Luiz Augusto von Dentz <luiz.von.dentz@intel.com>
2017-04-11 16:43:22 +03:00
Anas Nashif 50553dd700 debug: rename variable CONFIG_GDB_RAM_SIZE
CONFIG_* usually come from Kconfig, rename variables that are locally
defined to avoid confusion about where they are set.

Change-Id: I402713e6f852907e75be4bc2b916a7d15dd5649c
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2017-04-11 03:14:24 +00:00
Anas Nashif d7bc60f096 kernel: remove remaining microkernel references
Change-Id: Ie648dbaaf714316c21395bd43e555618013dbd19
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2017-04-10 20:21:05 +00:00
Piotr Mienkowski f33b277e6f drivers: i2c: rename I2C_CLOCK_SPEED Kconfig option
I2C_CLOCK_SPEED Kconfig option is DW driver specific. It does not
define I2C interface speed but rather the I2C DW module clock speed.
It is confusing for a user of any other I2C driver than DW.
This patch renames this option to I2C_DW_CLOCK_SPEED and makes it
visible only for DW I2C driver.

Change-Id: I97f57332fd5cca644eabdef0968a0b2174b885ff
Signed-off-by: Piotr Mienkowski <piotr.mienkowski@gmail.com>
2017-04-08 00:12:29 +00:00
Andrew Boie bf902e6b95 x86: add a more informative page fault handler
This is only built in if CONFIG_EXCEPTION_DEBUG is turned on.

Change-Id: I91f0601e344919f3481f7f5e78cb98c6784d1ec8
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2017-04-06 21:18:28 +00:00
Andrei Emeltchenko b973f987d8 quark_se: Fix Bluetooth settings for NBLE
Enable UART_QMSI_0 whenever NBLE is enabled the same way as it is done
for BLUETOOTH_H4.

Change-Id: Ib2f76f7e5e95620d40320891fec1b86509d1856e
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
2017-03-07 11:17:19 +00:00
Andrew Boie 3cc4d41438 ipm_console: add Kconfig for receiver stack size
Change-Id: I27c1189e3bf87b4ea3dc06d38f63cab21663697b
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2017-03-06 16:58:20 +00:00
Andy Ross 419fc7d473 quark_se: Fix bluetooth UART dependency
Fix c6e27a05 was too aggressive.  It turns out that bluetooth on the
Quark SE boards won't enable it's own UART, because it had always been
enabled.  Apps that don't do it already will be broken.

Enable UART_QMSI_0 whenever BLUETOOTH_H4 is pulled in on this
platform.

Change-Id: I5e21c6004714adba8fb0fafa056dc2d62698a3d1
Issue: ZEP-1788
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
2017-03-02 00:33:58 +00:00
Andy Ross c6e27a05c2 quark_se: Don't enable UART 0 always
The defconfigs would always create a device for UART 0, which is
problematic in circumstances where both the x86 and ARC cores are
alive and one wants to use it in a non-default configuration.

Specifically: on Arduino 101 this is the bluetooth device and it
operates at 1MBps instead of of 115200kbps.  If an x86 app sets this
up correctly, but then starts the ARC core running an app which
doesn't reference this UART at all, the device will still exist and
set up the (wrong!) configuration, clobbering the correct settings.

Just remove the "def-bool y" bits from the defconfig.  There's no
need, users of these devices (e.g. the console) will enable them
anyway.  There's no value to compiling it in without a configured
user.

Issue: ZEP-1677
Change-Id: I4a0e944f23705495433e9f3d0459065f131579cb
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
2017-02-22 22:42:25 +00:00
Anas Nashif fe118c4e95 license: replace APL2.0 license with SPDX
Some files made it through review process with full license header.

Change-Id: I2722b127c40b4b19500042c12e4fde85a165bae9
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2017-02-20 16:59:46 +00:00
Sarath R Nair 8ac992bfcd quark_se: Save/restore debug registers.
In order to set breakpoints after waking up from sleep,
it is needed to save DR0/DR1/DR2/DR3 and DR6/DR7.

As DR4/DR5 are reserved or mapped to DR6/DR7, they are not saved.

Patch2 : Added compile time checks for debug build or soc_watch
build for Intel Energy analysis.

Patch3 : Avoid clobbering of edx.

JIRA: ZEP-1681

Change-Id: I62fbedca16953d57196420ecae4fb93c785bb4a5
Signed-off-by: Sarath R Nair <sarath.nandu.ramachandran.nair@intel.com>
2017-02-11 00:15:08 +00:00
Jesus Sanchez-Palencia 98d4836105 linker quark_se: Fix operator precedence bug
Without this patch, the final linker script had a memory region defined
as:

    RAM (wx) : ORIGIN = 0xA8006400, LENGTH = 55*1K - 0x20 +0x4

resulting on the wrong RAM length. Fix BSP_SHARED_RAM_SIZE definition
so the sum is always processed first.

Change-Id: I16b93adbaf27bb84b6e5d1ac433ef80f854b218c
Signed-off-by: Jesus Sanchez-Palencia <jesus.sanchez-palencia@intel.com>
2017-02-09 19:58:45 +00:00
Andrew Boie d81e033044 build: Separate out prebuilt kernel logic from toplevel
Arch-specific stuff shouldn't be in the toplevel Makefile,
forthcoming patches will soon introduce special interrupt
handling logic for other arches.

Change-Id: Ib5a86cbdf5b32ecfce9e5e234f7cbea2bc3ce9c1
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2017-02-08 19:11:10 +00:00
Jesus Sanchez-Palencia a19d4ad041 quark_d2000: Add shared GDT memory to linker
A new shared memory area has been added to the QMSI bootloader in
order to store the GDT in RAM reliably.

Add the new entry to the QUARK D2000 linker script and new
kconfig options:

 * CONFIG_BSP_SHARED_GDT_RAM_ADDR to set the address location
   of the GDT in RAM.

 * CONFIG_BSP_SHARED_GDT_RAM_SIZE to set the size used by the
   GDT in RAM.

This is only enabled when  CONFIG_SET_GDT is NOT set.

Change-Id: Ie084079475853dce153dd9f3e88ad4a9784bdedf
Signed-off-by: Jesus Sanchez-Palencia <jesus.sanchez-palencia@intel.com>
2017-02-08 11:59:15 +00:00
Jesus Sanchez-Palencia bcee91d70e quark_se: Add shared GDT in RAM memory to linker
A new shared memory has been added to the QMSI bootloader in order to
store the GDT in RAM reliably.

Add this new entry to the QUARK SE C1000 linker script and new kconfig
options:

 * CONFIG_BSP_SHARED_GDT_RAM_ADDR to set the address location
   of the GDT in RAM.

 * CONFIG_BSP_SHARED_GDT_RAM_SIZE to set the size used by the
   GDT in RAM.

Additionally, both BSP_SHARED_RAM_ADDR and BSP_SHARED_RAM_SIZE have been
renamed to BSP_SHARED_RESTORE_INFO_RAM_ADDR and
BSP_SHARED_RESTORE_INFO_SIZE respectively, in order to better resemble
what these options are for. All these configs are available
unconditionally.

Change-Id: I07ee8b440d4a3f5e9bdeb62441ff6a7bd6d4c153
Signed-off-by: Jesus Sanchez-Palencia <jesus.sanchez-palencia@intel.com>
Signed-off-by: Bartlomiej Majka <bartlomiejx.majka@intel.com>
2017-02-08 11:59:14 +00:00
Jesus Sanchez-Palencia 78224e1a75 quark_se: Fix restore info address
For the next QMSI release, the shared restore info address has been
modified to 0xA8013FDC .

Change-Id: I72eaef4f15f7ef6fb8e7eb9acd7d96451623e103
Signed-off-by: Jesus Sanchez-Palencia <jesus.sanchez-palencia@intel.com>
2017-02-08 11:59:13 +00:00
Kuo-Lang Tseng 23b0074012 ext qmsi: Update to QMSI 1.4 RC2
Update the builtin QMSI code to 1.4 (RC2).
The below shim drivers were updated for API or interface changes:
- aio
- counter
- i2c_ss
- rtc
- wdt.

Also, arch soc specific power management code were updated.

Jira: ZEP-1572

Change-Id: Ibc8fae032a39ffb2c2c997f697835bc0208fd308
Signed-off-by: Jesus Sanchez-Palencia <jesus.sanchez-palencia@intel.com>
Signed-off-by: Kuo-Lang Tseng <kuo-lang.tseng@intel.com>
2017-02-08 11:59:12 +00:00
Andrew Boie e01dd87377 x86: implement direct interrupts
Change-Id: Icac461a361dde969f023e7aa11f0605a97a3c009
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2017-02-03 18:18:30 +00:00
Anas Nashif 42e1c9ca34 pinmux: make pinmux_dev the default pinmux driver for quark
Jira: ZEP-958
Change-Id: Ib6c528a103372d5084efa5ae8635803e2912e0dd
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2017-01-25 20:43:18 +00:00
Andre Guedes 6f141a5576 quark_se: PM: Add multicore support
This patch changes Quark SE power drivers to support multicore scenarios
e.g. both LMT and ARC core are enabled and manage power.

Handling LPS states in multicore scenarios are dead simple because LPS
states are core-specific states. It means that putting the LMT core in
LPS doesn't affect the ARC core, and vice-versa. DEEP_SLEEP state, on
the other hand, affects both cores since it turns power off from the SoC
and both cores are shutdown. It means that if LMT puts the system in
DEEP_SLEEP, ARC core is shutdown even if it is busy handling some task.

In order to support the multicore scenario, this patch introduces the
SYS_POWER_STATE_DEEP_SLEEP_2 state to both ARC and x86 power drivers.

On ARC, this state works as following:
1) Save ARC execution context;
2) Raise a flag to inform the x86 core that ARC is ready to enter in
   DEEP_SLEEP;
3) Enter in the lowest core-specific power state, which in this case is
   LPSS.

On x86, DEEP_SLEEP_2 is very similar to DEEP_SLEEP. The difference relies
in the post_ops() which calls _arc_init() in order to start ARC core so
it can restore its context.

This patch also adds the test/power/multicore/ directory which provides
sample application to x86 and ARC cores in order to easily verify the
multicore support. In test/power/multicore/README.rst you can find more
details regarding the applications.

Jira: ZEP-1103

Change-Id: Ie28ba6d193ea0e58fca69d38f8d3c38ca259a9ef
Signed-off-by: Andre Guedes <andre.guedes@intel.com>
2017-01-24 13:36:55 +00:00
Benjamin Walsh ee659ae1a1 build: add _ASMLANGUAGE to all asm files
This avoids asm files from having to explicitly define the _ASMLANGUAGE
symbol themselves.

Change-Id: I71f5a169f75d7443a58a0365a41c55b20dae3029
Signed-off-by: Benjamin Walsh <walsh.benj@gmail.com>
2017-01-24 13:34:51 +00:00
Benjamin Walsh ed240f2796 kernel/arch: streamline thread user options
The K_<thread option> flags/options avaialble to users were hidden in
the kernel private header files: move them to include/kernel.h to
publicize them.

Also, to avoid any future confusion, rename the k_thread.execution_flags
field to user_options.

Change-Id: I65a6fd5e9e78d4ccf783f3304b607a1e6956aeac
Signed-off-by: Benjamin Walsh <walsh.benj@gmail.com>
2017-01-24 13:34:50 +00:00
Benjamin Walsh 4b65502448 kernel/x86: move INT_ACTIVE/EXC_ACTIVE to thread_state
They are internal states, not user-facing.

Also prepend an underscore since they are kernel internal symbols.

Change-Id: I53740e0d04a796ba1ccc409b5809438cdb189332
Signed-off-by: Benjamin Walsh <walsh.benj@gmail.com>
2017-01-24 13:34:50 +00:00
Benjamin Walsh a8978aba8f kernel: rename thread states symbols
They are not part of the API, so rename from K_<state> to
_THREAD_<state>.

Change-Id: Iaebb7d3083b80b9769bee5616e0f96ed2abc5c56
Signed-off-by: Benjamin Walsh <walsh.benj@gmail.com>
2017-01-24 13:34:49 +00:00
David B. Kinder ac74d8b652 license: Replace Apache boilerplate with SPDX tag
Replace the existing Apache 2.0 boilerplate header with an SPDX tag
throughout the zephyr code tree. This patch was generated via a
script run over the master branch.

Also updated doc/porting/application.rst that had a dependency on
line numbers in a literal include.

Manually updated subsys/logging/sys_log.c that had a malformed
header in the original file.  Also cleanup several cases that already
had a SPDX tag and we either got a duplicate or missed updating.

Jira: ZEP-1457

Change-Id: I6131a1d4ee0e58f5b938300c2d2fc77d2e69572c
Signed-off-by: David B. Kinder <david.b.kinder@intel.com>
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2017-01-19 03:50:58 +00:00
Anas Nashif 6bea1becab build: move qemu definitions to boards
Change-Id: I4e87dbd6eea8320f23e5691c1762a7353240a5c8
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2017-01-10 20:20:47 +00:00
Benjamin Walsh 168695c7ef kernel/arch: inspect prio/sched_locked together for preemptibility
These two fields in the thread structure control the preemptibility of a
thread.

sched_locked is decremented when the scheduler gets locked, which means
that the scheduler is locked for values 0xff to 0x01, since it can be
locked recursively. A thread is coop if its priority is negative, thus
if the prio field value is 0x80 to 0xff when looked at as an unsigned
value.

By putting them end-to-end, this means that a thread is non-preemptible
if the bundled value is greater than or equal to 0x0080. This is the
only thing the interrupt exit code has to check to decide to try a
reschedule or not.

Change-Id: I902d36c14859d0d7a951a6aa1bea164613821aca
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
2017-01-09 20:52:25 +00:00
Benjamin Walsh f955476559 kernel/arch: optimize memory use of some thread fields
Some thread fields were 32-bit wide, when they are not even close to
using that full range of values. They are instead changed to 8-bit fields.

- prio can fit in one byte, limiting the priorities range to -128 to 127

- recursive scheduler locking can be limited to 255; a rollover results
  most probably from a logic error

- flags are split into execution flags and thread states; 8 bits is
  enough for each of them currently, with at worst two states and four
  flags to spare (on x86, on other archs, there are six flags to spare)

Doing this saves 8 bytes per stack. It also sets up an incoming
enhancement when checking if the current thread is preemptible on
interrupt exit.

Change-Id: Ieb5321a5b99f99173b0605dd4a193c3bc7ddabf4
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
2017-01-09 20:52:24 +00:00
Benjamin Walsh d779f3d240 kernel/arch: streamline thread flag bits used
Use least significant bits for common flags and high bits for
arch-specific ones.

Change-Id: I982719de4a24d3588c19a0d30bbe7a27d9a99f13
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
2017-01-06 17:32:24 +00:00
Benjamin Walsh e6a69cae54 kernel/arch: reverse polarity on sched_locked
This will allow for an enhancement when checking if the thread is
preemptible when exiting an interrupt.

Change-Id: If93ccd1916eacb5e02a4d15b259fb74f9800d6f4
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
2017-01-06 17:32:24 +00:00
Anas Nashif fad7e2dd8d logging: move event_logger to subsys/logging
Jira: ZEP-1337
Change-Id: If1690e19a882cf53caaa3418ccabeb49c783f63d
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-12-25 14:34:43 -05:00
Anas Nashif c1347b4730 kernel: replace all remaining nanokernel occurances
replace include <nanokernel.h> with <kernel.h> everywhere and also fix
any remaining mentions of nanokernel.

Keep the legacy samples/tests as is.

Change-Id: Iac48447bd191e83f21a719c69dc26233216d08dc
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-12-25 14:34:43 -05:00
Benjamin Walsh bfa5653e9a arch: remove instances of fiberRtnValueSet()
Obsolete, replaced by _set_thread_return_value().

Change-Id: I23e9cfc07e43542f0965817edc3552d456fd2ef3
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
2016-12-21 19:50:08 +00:00
Anas Nashif 87133d5def debug: gdb: move to new kernel APIs
Change-Id: Ifed1fe7c60fa150ee3ef4fefabafeb95312bf8bc
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-12-19 14:59:35 -05:00
Anas Nashif d687a95611 kernel: move kernel code to kernel/ directly
Also remove mentions of unified kernel in various places in the kernel,
samples and documentation.

Change-Id: Ice43bc73badbe7e14bae40fd6f2a302f6528a77d
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-12-19 14:59:35 -05:00
Anas Nashif 0d775bcd9c x86: remove obsolete comment about tasks/fibers
Change-Id: Iff911329f5c981d0d47880924e8a4d52478423fd
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-12-19 19:58:42 +00:00
Anas Nashif 569f0b4105 debug: move debug features from misc to subsys/debug
Change-Id: I446be0202325cf3cead7ce3024ca2047e3f7660d
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-12-19 19:58:40 +00:00
Anas Nashif a9e879e273 logging: move sys_log to subsys/logging
Move logging out of misc/ to its own subsystem. Anything related to
logging and any new logging features or backends could be added here
instead of the generic location in misc/ which is overcrowded with
options that are not related to eachother.

Jira: ZEP-1467
Change-Id: If6a3ea625c3a3562a7a61a0ba5fd7e6ca75518ba
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-12-19 19:58:39 +00:00
Anas Nashif f855d3558f kernel: remove unused and obsolete headers
Change-Id: I25fd7c9e3db2d171a4118a57c4d9544d2424b819
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-12-19 19:58:03 +00:00
Anas Nashif cb888e6805 kernel: remove nano/micro wording and usage
Also remove some old cflags referencing directories that do not exist
anymore.
Also replace references to legacy APIs in doxygen documentation of
various functions.

Change-Id: I8fce3d1fe0f4defc44e6eb0ae09a4863e33a39db
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-12-19 19:58:03 +00:00
Benjamin Walsh 48db0b3443 arch/all: simpler _SysFatalErrorHandler()
- does not pull in printk(), for potential footprint gain
- does not pull in k_thread_abort(), for single-threaded systems

Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
Change-Id: Ibc6a198b81a6cd73117d1e85aa05b92a4501a34d
2016-12-15 16:17:39 -05:00
Benjamin Walsh 8e4a534ea1 kernel: enable and optimize coop-only configurations
Some kernel operations, like scheduler locking can be optmized out,
since coop threads lock the scheduler by their very nature. Also, the
interrupt exit path for all architecture does not have to do any
rescheduling, again by the nature of non-preemptible threads.

Change-Id: I270e926df3ce46e11d77270330f2f4b463971763
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
2016-12-15 16:17:38 -05:00
Benjamin Walsh c3a2bbba16 kernel: add k_cpu_idle/k_cpu_atomic_idle()
nano_cpu_idle/nano_cpu_atomic_idle were not ported to the unified
kernel, and only the old APIs were available. There was no real impact
since, in the unified kernel, only the idle thread should really be
doing power management. However, with a single-threaded kernel, these
functions can be useful again.

The kernel internals now make use of these APIs instead of the legacy
ones.

Change-Id: Ie8a6396ba378d3ddda27b8dd32fa4711bf53eb36
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
2016-12-15 16:17:38 -05:00
Benjamin Walsh 88b3691415 kernel/arch: enhance the "ready thread" cache
The way the ready thread cache was implemented caused it to not always
be "hot", i.e. there could be some misses, which happened when the
cached thread was taken out of the ready queue. When that happened, it
was not replaced immediately, since doing so could mean that the
replacement might not run because the flow could be interrupted and
another thread could take its place. This was the more conservative
approach that insured that moving a thread to the cache would never be
wasted.

However, this caused two problems:

1. The cache could not be refilled until another thread context-switched
in, since there was no thread in the cache to compare priorities
against.

2. Interrupt exit code would always have to call into C to find what
thread to run when the current thread was not coop and did not have the
scheduler locked. Furthermore, it was possible for this code path to
encounter a cold cache and then it had to find out what thread to run
the long way.

To fix this, filling the cache is now more aggressive, i.e. the next
thread to put in the cache is found even in the case the current cached
thread is context-switched out. This ensures the interrupt exit code is
much faster on the slow path. In addition, since finding the next thread
to run is now always "get it from the cache", which is a simple fetch
from memory (_kernel.ready_q.cache), there is no need to call the more
complex C code.

On the ARM FRDM K64F board, this improvement is seen:

Before:

1- Measure time to switch from ISR back to interrupted task

   switching time is 215 tcs = 1791 nsec

2- Measure time from ISR to executing a different task (rescheduled)

   switch time is 315 tcs = 2625 nsec

After:

1- Measure time to switch from ISR back to interrupted task

   switching time is 130 tcs = 1083 nsec

2- Measure time from ISR to executing a different task (rescheduled)

   switch time is 225 tcs = 1875 nsec

These are the most dramatic improvements, but most of the numbers
generated by the latency_measure test are improved.

Fixes ZEP-1401.

Change-Id: I2eaac147048b1ec71a93bd0a285e743a39533973
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
2016-12-15 15:50:02 -05:00
Flavio Santes 59c8f32f0f x86/soc: Add ARG_UNUSED macro to avoid compiler warnings
The ARG_UNUSED macro is added to avoid compiler warnings.

Change-Id: If0242548849ee5b258bb3fce9fd727b377411343
Signed-off-by: Flavio Santes <flavio.santes@intel.com>
2016-12-12 20:02:30 +00:00
Flavio Santes 91aa33ba11 arch/x86: Remove unused parameter warning
This patch fixes the unused parameter warning found at the
quark_x1000/soc.h file.

Change-Id: I110d7185d8302f95d14efd13060055e7378aea23
Signed-off-by: Flavio Santes <flavio.santes@intel.com>
2016-12-03 14:49:10 +00:00
Andrew Boie 452fd7a5c2 x86: don't set segment registers if we don't set GDT
We have no idea what's in the GDT if we don't set it ourself.

Change-Id: I3c2e406370e3ea149252c423d66c97aab95bee17
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2016-11-29 14:51:57 -08:00
Ramesh Thomas 4a09593714 quark_se: power_mgmt: Fixes a cpu context save bug
The cpu context save function was manipulating stack and
returning to C caller. This can corrupt stack if the calling
function has data saved and it pops before entering deep
sleep. Moved sleep functions into assembly to avoid this.

Jira: ZEP-1345
Change-Id: I8a6d279ec14e42424f764d9ce8cbbef32149fe84
Signed-off-by: Ramesh Thomas <ramesh.thomas@intel.com>
2016-11-28 00:59:51 +00:00
Benjamin Walsh b2974a666d kernel/arch: move common thread.flags definitions to common file
Also remove NO_METRIC, which is not referenced anywhere anymore.

Change-Id: Ieaedf075af070a13aa3d975fee9b6b332203bfec
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
2016-11-26 14:04:18 +00:00
Benjamin Walsh 069fd3624e kernel: streamline initialization of _thread_base and timeouts
Move _thread_base initialization to _init_thread_base(), remove mention
of "nano" in timeouts init and move timeout init to _init_thread_base().
Initialize all base fields via the _init_thread_base in semaphore groups
code.

Change-Id: I05b70b06261f4776bda6d67f358190428d4a954a
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
2016-11-23 00:27:42 +00:00
Benjamin Walsh 8fcc7f69da kernel/arch: remove unused uk_task_ptr parameter from _new_thread()
Artifact from microkernel, for handling multiple pending tasks on
nanokernel objects.

Change-Id: I3c2959ea2b87f568736384e6534ce8e275f1098f
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
2016-11-23 00:23:57 +00:00
Andrew Boie 2ffa516d89 x86: set accessed bit in ROM-based GDT
Previous configuration was backwards. From the Intel manual:

"If the segment descriptors in the GDT or an LDT are placed in ROM,
the processor can enter an indefinite loop if software or the
processor attempts to update (write to) the ROM-based segment
descriptors. To prevent this problem, set the accessed bits
for all segment descriptors placed in a ROM. Also, remove
operating-system or executive code that attempts to modify
segment descriptors located in ROM."

Only by some miracle has this not been causing problems.

Change-Id: I0bb915962a1069876d2486473760112102feae7b
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2016-11-19 00:57:04 +00:00
Benjamin Walsh 669360d5ec kernel: fix thread prio and stack size types in some APIs
Prio should be an int, since values are small integers, not a fixed-size
int32_t. It aligns with the prio parameters of the other APIs.

Stack size should be size_t.

Change-Id: Id29751b86c4ad7a7c2a7ffe446c2a96ae83c77bf
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
2016-11-18 23:08:46 +00:00
Inaky Perez-Gonzalez 11bd718733 fatal error handlers: report which thread croaked
When a thread dies, at least print the pointer to it, so we can debug
better.

Change-Id: Ief6bbc0c221e2d5271c240a4b73df16413aa5e22
Signed-off-by: Inaky Perez-Gonzalez <inaky.perez-gonzalez@intel.com>
2016-11-17 14:36:50 +00:00
Allan Stephens c98da84e69 doc: Various corrections to doxygen info for Kernel APIs
Most kernel APIs are now ready for inclusion in the API guide.
The APIs largely follow a standard template to provide users
of the API guide with a consistent look-and-feel.

Change-Id: Ib682c31f912e19f5f6d8545d74c5f675b1741058
Signed-off-by: Allan Stephens <allan.stephens@windriver.com>
2016-11-16 21:43:16 +00:00
Anas Nashif 2367df8d59 drivers: update ipm driver to use unified kernel
Move away from legacy APIs and use unified kenrel instead.

Change-Id: Icae86beec66df1b041405cbe3455913630fc8ad1
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-11-13 13:53:53 +00:00
Benjamin Walsh f6ca7de09c kernel/arch: consolidate tTCS and TNANO definitions
There was a lot of duplication between architectures for the definition
of threads and the "nanokernel" guts. These have been consolidated.

Now, a common file kernel/unified/include/kernel_structs.h holds the
common definitions. Architectures provide two files to complement it:
kernel_arch_data.h and kernel_arch_func.h. The first one contains at
least the struct _thread_arch and struct _kernel_arch data structures,
as well as the struct _callee_saved and struct _caller_saved register
layouts. The second file contains anything that needs what is provided
by the common stuff in kernel_structs.h. Those two files are only meant
to be included in kernel_structs.h in very specific locations.

The thread data structure has been separated into three major parts:
common struct _thread_base and struct k_thread, and arch-specific struct
_thread_arch. The first and third ones are included in the second.

The struct s_NANO data structure has been split into two: common struct
_kernel and arch-specific struct _kernel_arch. The latter is included in
the former.

Offsets files have also changed: nano_offsets.h has been renamed
kernel_offsets.h and is still included by the arch-specific offsets.c.
Also, since the thread and kernel data structures are now made of
sub-structures, offsets have to be added to make up the full offset.
Some of these additions have been consolidated in shorter symbols,
available from kernel/unified/include/offsets_short.h, which includes an
arch-specific offsets_arch_short.h. Most of the code include
offsets_short.h now instead of offsets.h.

Change-Id: I084645cb7e6db8db69aeaaf162963fe157045d5a
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
2016-11-12 07:04:52 -05:00
Jithu Joseph fca0add22b console : usb: USB UART console output support
Add support for console output via the USB UART.
Note that console input via the USB UART doesnt work.

Adds a simulated poll method for UART interface exposed by USB.

Jira : ZEP-775

Change-Id: I357827ea52c027eb000baed80225f422df1f3358
Signed-off-by: Jithu Joseph <jithu.joseph@intel.com>
2016-11-12 01:39:30 +00:00
Ramesh Thomas 24f94ca49e quark-se: power_mgmt: Add a optional deep sleep resume handler
Some arduino 101 boards have old boot loader without context
restore boot flow feature. This handler will allow doing deep sleep
in those boards by jumping to the context restore code. This will
be disabled by default and can be optionally enabled by user.

Jira: ZEP-1258
Change-Id: I92e70550fd92c1cac42b3039d667fb0be8cf5bce
Signed-off-by: Ramesh Thomas <ramesh.thomas@intel.com>
2016-11-11 20:41:52 +00:00
Ramesh Thomas a3dc53f2a6 power_mgmt: Do not notify deep sleep if bootloader does context restore
Some bootloaders have power management support to restoer context
upon resume from deep sleep. In such cases, the OS startup code
should call the notification hook. Create Kconfig flags to configure
this option.

Jira: 1257
Change-Id: I9f40c5fa077c2f17dc8e9f11604c3ed17e549ed5
Signed-off-by: Ramesh Thomas <ramesh.thomas@intel.com>
2016-11-11 20:40:53 +00:00
Ramesh Thomas c0cd7acf34 power_mgmt: Simplify _sys_soc_resume notification
_sys_soc_resume hook is over loaded to handle to different
scenarios. It is primarily called to notify exit of kernel idling
after PM operations. It is also used to notify exit from deep sleep.
This is very confusing and also makes the implementation of the
hook function very difficult because of very different conditions
involved in the 2 different use cases. Further, users may not require
either or both use cases depending of their custom boot flow and
power state handling. To simplify, create a separate hook for the
purpose of deep sleep exit notification. Use the existing one to
only notify kernel idling exit after PM operations.

Jira: ZEP-1256
Change-Id: I96350199a0fd37f16590c8ee5302a94a3d71b8ba
Signed-off-by: Ramesh Thomas <ramesh.thomas@intel.com>
2016-11-11 20:40:52 +00:00
Julien Delayen 6e71f1f6a3 power: Fix x86 wake up sequence
When waking up from C2LP state, the timer needs
to be reinitialized as we cannot know the time
that we spent in that state.
In order to reschedule the user application, expire it
as soon as we restart.

Change-Id: Id38a0de71e148ae8d9024a36d3983ab57b1e40d2
Signed-off-by: Julien Delayen <julien.delayen@intel.com>
2016-11-11 03:29:02 +00:00
Anas Nashif 7cac3b9625 arch: arc: arm: sys_thread_self_get -> k_current_get
Change-Id: Iaa01b0d8733d76888524cfd258bacbd9c11142de
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-11-10 18:52:51 +00:00
Allan Stephens bce8fbb61e kernel: Clean up of x86 floating point code
Updates x86 floating point support to reflect changes that have
been made in recent months.

* Many, many, many cosmetic changes (mostly revisions to comments).

* Elimination of unnecessary function aliases that were needed
  to support the task and fiber versions of certain APIs.

* Elimination of run-time code to enable a thread's "FP regs"
  option bit if the "SSE regs" option bit was set. The kernel
  now recognizes that the thread is using the FPU as long as
  either option bit is set. (If the thread has both option bits
  enabled this is the same as if only the "SSE regs" bit is set.)

Change-Id: Ic12abc54b6fa78921749b546d8debf23e7ad232d
Signed-off-by: Allan Stephens <allan.stephens@windriver.com>
2016-11-09 23:51:30 +00:00
Andrew Boie 56f561e15e arches: use new kernel APIs
Change-Id: I4b6f5264d5295ebf4278991a1f4e2141bef6602f
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2016-11-09 20:49:40 +00:00
Andrew Boie 0b474eef9c kernel: deprecate old init levels
PRIMARY, SECONDARY, NANOKERNEL, MICROKERNEL init levels are now
deprecated.

New init levels introduced: PRE_KERNEL_1, PRE_KERNEL_2, POST_KERNEL
to replace them.

Most existing code has instances of PRIMARY replaced with PRE_KERNEL_1,
SECONDARY with POST_KERNEL as SECONDARY has had a longstanding bug
where the documentation specified SECONDARY ran before the kernel started
up, but actually ran afterwards.

Change-Id: I771bc634e9caf7f17dbf214a270bc9967eed7d32
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2016-11-09 17:59:44 +00:00
Benjamin Walsh 3cc2ba9f9c kernel: add __ASSERT() for thread priorities
Verify the thread priorities are within the bounds when starting a new
thread and when changing the priority of a thread.

Change-Id: I007b3b249e4b80235b6439cbee44cad2f31973bb
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
2016-11-08 20:27:31 -05:00
Andrew Boie ee95dd22a4 x86: remove CONFIG_NANOKERNEL references
Change-Id: I8c6ca9189dd09133162816675e33332d6e5a34b3
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2016-11-08 22:02:45 +00:00
Leandro Pereira 0be498db5c quark_se: Correctly wait for ARC_READY flag while initializing ARC
The bitwise AND operator was being applied to the boolean expression
"!shared_data->flags" instead of the whole expression because a
parenthesis was lacking.

This bug has been found using Coccinelle using the following spatch,
after finding a similar bug somewhere else in the code base:

      @@
      expression E1;
      expression E2;
      @@

      - !E1 & E2
      + !(E1 & E2)

No other instance of this defect has been found with this spatch.

Change-Id: I6b9ca092f4015c80ddc83c31ce540a92e67cdb11
Signed-off-by: Leandro Pereira <leandro.pereira@intel.com>
2016-11-07 22:22:00 +00:00
Allan Stephens f48f263665 kernel: Rename USE_FP and USE_SSE symbols
Symbols now use the K_ prefix which is now standard for the
unified kernel. Legacy support for these symbols is retained
to allow existing applications to build successfully.

Change-Id: I3ff12c96f729b535eecc940502892cbaa52526b6
Signed-off-by: Allan Stephens <allan.stephens@windriver.com>
2016-11-07 18:52:31 +00:00
Anas Nashif 12ffc58d4b benchmarks: rename _NanoTscRead -> _tsc_read
Change-Id: Id5687f79ac13136f14a14d250e149436a0173f04
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-11-07 15:39:15 +00:00
Andrew Boie 6e172b8abd x86: remove legacy kernel support
Change-Id: I81111a58d1305bd521ea93adc40c66b43f20977c
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2016-11-04 11:45:13 -07:00
Allan Stephens a3f3de3741 unified: Rename ESSENTIAL to K_ESSENTIAL
Adds standard prefix to symbolic option that flags a thread
as essential to system operation.

Change-Id: Ia904a81ce343fdd1cd44caaaeae641d822777f9b
Signed-off-by: Allan Stephens <allan.stephens@windriver.com>
2016-11-04 00:47:08 +00:00
Julien Delayen fec01af64a power: Update Quark SE PM layer with QMSI 1.3
QMSI 1.3 natively supports restoring the SoC and peripherals
after sleep.

The Zephyr Power Management shim layer is updated
in order to support QMSI functions.

The following functions have been added:
void _sys_soc_set_power_state(enum power_state);
void _sys_soc_power_state_post_ops(void);

In order to fully support deep sleep, the function
_sys_soc_set_power_state now support saving and
restoring CPU context and returns to the application.

_sys_soc_set_power_state function also abstracts
QMSI cpu states and enable the application to choose
between C1/C2 or C2LP states.

The QMSI power states are mapped as follows:
SYS_SOC_POWER_STATE_CPU_LPS -> power_cpu_c2lp
SYS_SOC_POWER_STATE_CPU_LPS_1 -> power_cpu_c2
SYS_SOC_POWER_STATE_CPU_LPS_2 -> power_cpu_c1
SYS_SOC_POWER_STATE_DEEP_SLEEP -> power_soc_deep_sleep
SYS_SOC_POWER_STATE_DEEP_SLEEP_1 -> power_soc_sleep

The following functions have been removed:
void _sys_soc_set_power_policy(uint32_t pm_policy);
int _sys_soc_get_power_policy(void);
FUNC_NORETURN void _sys_soc_put_deep_sleep(void);
void _sys_soc_put_low_power_state(void);
void _sys_soc_deep_sleep_post_ops(void);

Those changes are propagated to the samples.
All calls to QMSI are removed.

Jira: ZEP-1045, ZEP-993, ZEP-1047

Change-Id: I26822727985b63be0a310cc3590a3e71b8e72c8c
Signed-off-by: Julien Delayen <julien.delayen@intel.com>
Signed-off-by: Ramesh Thomas <ramesh.thomas@intel.com>
2016-11-03 21:31:30 +00:00
Julien Delayen 5e87553079 quark_se: Add restore info shared memory to linker
A new shared memory has been added to the qmsi bootloader
in order to handle the restore flow and jump to
the restore trap where context is restored.

Add the new entry to the QUARK SE C1000 linker file
and new kconfig options:
- CONFIG_BSP_SHARED_RAM_ADDR to set the address of the
  shared memory.
- CONFIG_BSP_SHARED_RAM_SIZE to set the size of the
  shared memory.

This is only enabled with CONFIG_SYS_POWER_DEEP_SLEEP.

Jira: ZEP-1046

Change-Id: I35d924a100c5583025aa36a9741428ab51809c57
Signed-off-by: Julien Delayen <julien.delayen@intel.com>
2016-11-03 21:31:26 +00:00
Iván Briano beb4f405d8 socs quark: Simplify IRQ configuration
IRQ numbers differ between x86 and ARC, as well as the bits that need to
be touched in the interrupt routing masks. QMSI abstracts some of it and
for the rest we do have the information needed.

Add a macro to select the right IRQ number based on which core we are
building for.

Change-Id: I3e6680d10a0a23c98777d2831efe6819fcb54162
Signed-off-by: Iván Briano <ivan.briano@intel.com>
2016-11-02 22:24:27 +00:00
Andrew Boie 4208976bfc build: consolidate some common parts of linker scripts
There are a number of data sections that are repeated across
all the linker scripts for various architecture. In practice these
don't always get updated and we have had problems with bit-rot.
Consolidate these to make maintenance easier.

x86 linker scripts now follow the same naming convention and we
get rid of a linker-epilog.h that wasn't necessary and whose purpose
has been lost to the mists of time. If applications want to define their
own sections they should be allowed to. Linker scripts for x86 do not
end with .h any more, they are not C header files even though we use
C's preprocessor.

Issue: ZEP-688
Change-Id: I893eb4619969695c1f980efd7c2ec9fa5dad136d
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2016-10-31 18:00:58 -07:00
Iván Briano 0094ab228d ext qmsi: Update to QMSI 1.3 release
Update the QMSI drop we maintain in Zephyr, and fix the build where
needed:

- QM_SCSS_INT is renamed to QM_INTERRUPT_ROUTER;
- every member of QM_INTERRUPT_ROUTER was renamed as well;
- QM_IRQ_* renamed too, mostly added _INT at the end;
- some isr functions were renamed to keep their names consistent;
- build for x86 needs to define QM_LAKEMONT, as QM_SENSOR was for ARC.

Change-Id: I459029ca0d373f6c831e2bb8ebd52402a55994d1
Signed-off-by: Iván Briano <ivan.briano@intel.com>
2016-10-31 13:26:06 +00:00
Benjamin Walsh b452817b67 kernel: merge _IS_IN_ISR() with _is_in_isr()
They were the same, standardize on the lowercase one.

Change-Id: I8bca080e45f3e0970697d4451e468b9081f96f5f
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
2016-10-27 21:45:03 +00:00
Allan Stephens 743bdb8143 unified: Enable handling of thread options for static threads
Change-Id: I51d2d9cfa0eeb5f974a6cf1db32406399ef57418
Signed-off-by: Allan Stephens <allan.stephens@windriver.com>
2016-10-27 08:36:14 -05:00
Allan Stephens 2220f25f0a kernel: Standardize thread monitoring initialization
Gets rid of unnecessary THREAD_MONITOR_INIT() macro, to be
consistent with the approach taken by _thread_monitor_exit().

Aligns x86 code with the approach used on other architectures.

Revises the associated comments and removes unnecessary
doxygen tags.

Change-Id: Ied1aebcd476afb82f61862b77264efb8a7dc66c9
Signed-off-by: Allan Stephens <allan.stephens@windriver.com>
2016-10-26 17:03:12 +00:00
Anas Nashif 641944283d soc: intel_quark: source Kconfig file of SoC
Change-Id: Ibcd8dc5889cc89333a017d2838294e6abf16618a
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-10-22 16:55:54 -04:00
Anas Nashif dc8f7b1573 quark d2000: remove bluetooth configuration from SoC
Bluetooth is not an SoC feature of the D2000.

Change-Id: Ibc8a8e6986a7da227fc42cb833fe8508696b104a
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-10-17 09:51:39 +00:00
Marcus Shawcroft 14aa67cbd1 board: Enable ETH_DW for quark_x1000 if ETHERNET is enabled.
There is a convention in the soc implementation for other
(non-ethernet) classes of driver that enabling a generic driver has the
effect of enabling the specific flavour of driver required for the
board.  Extend this convention such that when ETHERNET is enabled, the
quark_x1000 enables the DW ethernet driver.

Change-Id: I525471d259c9582024cd44d6cc4557260abe6451
Signed-off-by: Marcus Shawcroft <marcus.shawcroft@arm.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-10-15 16:44:06 +00:00
Marcus Shawcroft c5248a9d26 quark_se: Make ipm console config structure static.
Change-Id: Id8c4c94a76c5a5f7d2a1bcef2059511033f65ee8
Signed-off-by: Marcus Shawcroft <marcus.shawcroft@arm.com>
2016-10-15 12:29:24 +00:00
Benjamin Walsh 35497d6c5e unified: cache the next thread to run
When adding a thread to the ready queue, it is often known at that time
if the thread added will be the next one to run or not. So, instead of
simply updating the ready queues and the bitmask, also cache what that
thread is, so that when the scheduler is invoked, it can simply fetch it
from there. This is only done if there is a thread in the cache, since
the way the cache is updated is by comparing the priorities of the
thread being added and the cached thread.

When a thread is removed from the ready queue, if it is currently the
cached thread, it is also removed from the cache. The cache is not
updated at this time, since this would be a preemptive fetching that
could be overriden before the newly cached thread would even be
scheduled in.

Finally, when a thread is scheduled in, it now becomes the cached thread
since the fact that it is running means that by definition it was the
next one to run.

Doing this can speed up considerably some context switch times,
especially when a thread is preempted by an interrupt and the same
thread is scheduled when the interrupt exits.

Change-Id: I6dc8391cfca566699bb9b217eafe6bc6a063c8bb
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
2016-10-10 21:27:31 +00:00
Anas Nashif 5e5981234f quark_se: x86 core does not support ADC
ADC is available on the sensor subsystem only.

Change-Id: I3242108eb1f39a9509e30cc7ff440e02811ba4e6
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-10-10 21:26:31 +00:00
Anas Nashif 37d2fdce13 quark: dma: enable qmsi driver if DMA is selected
Change-Id: I413dc28da562a7899c5271a36eca9a6d8d84221a
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-10-10 21:26:29 +00:00
Anas Nashif 84c9db39e7 gpio: reduce Kconfigs and use consistent name for GPIOs
Using AON for GPIO kconfigs is very specifc to quark se, there
is no need to make this special for this platform. Use the
existing scheme instead.

Change-Id: I946431490380dc0f537d6056277a94c9c9c80fed
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-10-07 16:15:07 +00:00
Ramesh Thomas c4c0ed414b power_mgmt: Reduce complexity in handling of power hooks
Simplified some documentation, removing inconsistencies and making
it easier to understand by separating PM infrastructure areas and
soc specific components that implement the hooks.

Removed the DEVICE_SUSPEND_ONLY policy as it is redundant and
causes high complexity in the flow. It is also not practical
to use it because it was meant to be used without doing CPU or SOC
low power state operations. This means it would do device PM
operations in the ISR of the system timer used by the scheduler.
This can disrupt the scheduler time.

Added a check of a flag around the notification sent from the ISR
of the wake event and created APIs to set/clear it. This will
allow disabling the notification when not needed from
_sys_soc_suspend().

Jira: ZEP-972
Change-Id: Id7aa7d2683384eabed518d4efac446ecc84c3498
Signed-off-by: Ramesh Thomas <ramesh.thomas@intel.com>
2016-10-05 10:05:42 +00:00
Andrew Boie 26b1651f0c intstub.S: fix argument to _sys_power_save_idle_exit on IAMCU
Change-Id: I5aa1abe464ba2b8f9c36be78a95705ffcf993c7d
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2016-09-28 20:28:27 +00:00
Andrew Boie 70d8a32740 x86: interrupts: consolidate duplicated code in idle path
Change-Id: I16b80f363fef17d3ea99fec0ced4f49238f8e6c7
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2016-09-28 20:28:07 +00:00
Andrew Boie e56f61f5aa x86: exceptions: simplify exception stubs
Exception stubs now just push the handler and in some cases a dummy
error code before jumping to the exception handling code, never to
return.

Change-Id: I6a79d9243deb3fc7ccdae003dd0917364c0aa304
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2016-09-28 20:28:07 +00:00
Andrew Boie edeb1f1c52 x86: interrupts: optimize and simplify IRQ stubs
Interrupt stubs now just push the ISR and parameter onto the stack
and jump to the common interrupt code, never to return.

Change-Id: I82543d8148b5c7dfe116c43f41791f852614bb28
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2016-09-28 20:28:06 +00:00
Andrew Boie 2d7490c7ce x86: don't unconditionally run ISRs with interrupts enabled
Re-enabling interrupts before running the ISR must only be done
when CONFIG_NESTED_INTERRUPTS is turned on.

Change-Id: I2c04f2ce08d41cfef5553ee8554a90d1be0e86a3
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2016-09-26 17:53:45 +00:00
Peter Mitsis b27249486a unified: Remove references to obsolete task_timeout
Change-Id: I7c3b1b8418809914d3daf9d68ed8e4c3b99dd0b1
Signed-off-by: Peter Mitsis <peter.mitsis@windriver.com>
2016-09-23 19:53:20 +00:00
Andrew Boie 99368c7435 x86: optimize GDT space
The CPU manual indicates that 8-byte alignment is sufficient,
not sure why gdt_rom was aligned on a 16-byte boundary.

The null descriptor in the GDT is never looked at by the CPU,
save a few bytes by putting the 6-byte pseudo descriptor there.

Change-Id: I73f26cdeb30a91f8258c88ef960a45812a11d959
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2016-09-20 20:47:15 +00:00
Andrew Boie 757dae5b7d x86: introduce new segmentation.h header
This header has a bunch of data structure definitions and macros useful
for manipulating segment descriptors on X86. The old IDT_ENTRY defintion
is removed in favor of the new 'struct segment_descriptor' which can be
used for all segment descriptor types and not just IRQ gates.

We also add some inline helper functions for examining segment registers,
descriptor tables, and doing far jumps/calls.

Change-Id: I640879073afa9765d2a214c3fb3c3305fef94b5e
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2016-09-20 20:46:45 +00:00
Peter Mitsis 3ffe5bfb8c unified: Include _timeout structure in tcs_base
The '_timeout' structure is needed by dummy threads so that they can
handle timeouts.

Change-Id: Iefabd6ad93c8e176e95ce4262f5f3544dc90b7d5
Signed-off-by: Peter Mitsis <peter.mitsis@windriver.com>
2016-09-20 11:43:40 -04:00
Peter Mitsis 68d1f4b562 unified: Add timeslice support
Change-Id: I5b6c1ef5c015d1ddaea21b1c5447336b1b04db39
Signed-off-by: Peter Mitsis <peter.mitsis@windriver.com>
2016-09-20 15:28:54 +00:00
Anas Nashif 442987f542 intel_quark: move X86_IAMCU to defconfig
Do not force selection of X86_IAMCU

Jira: ZEP-867
Change-Id: I2ca0bcd73502321e9e6f5a4638c309393da54e43
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-09-17 11:14:12 +00:00
Anas Nashif 99abf49fce quark_x1000: move the X1000 into the intel_quark family
Change-Id: I9d7f1bc56293458d1410b40b7e103974718cb681
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-09-16 03:10:33 +00:00
Anas Nashif 211e0e14d7 soc: intel_quark: move quark d2000 to intel_quark family
Change-Id: I4eeb25ee3ee94d59e6425163aad3c393593b7e02
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-09-16 03:10:32 +00:00
Anas Nashif 0be112fbcb intel_quark: Group Quark SoCs under intel_quark/
Change-Id: If0120aff88310871438562234abf51b26675ff28
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-09-16 03:10:32 +00:00
Anas Nashif 5363d14a9e boards: rename Quark SE Devboard to Quark SE C1000
This board now has an official name and will be available soon:

http://www.intel.com/content/www/us/en/embedded/products/quark/mcu/se-soc/overview.html

Jira: ZEP-758
Change-Id: Ia16d33722308cf81471321c3063bdc75055a4d50
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-09-16 03:10:31 +00:00
Anas Nashif 5e4b62c35c boards: rename Quark SE Devboard to Quark SE C1000 (Sensor Subsystem)
Jira: ZEP-758
Change-Id: I8ee5a2f9e4a6ecbd15214e59321bf27a502ef6ee
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-09-16 03:10:30 +00:00