Commit graph

4 commits

Author SHA1 Message Date
Kumar Gala
6ae8664889 drivers: i2s: i2s_sam_ssc: Convert to devicetree
Convert i2s_sam_ssc driver to utilize devicetree.  We replace Kconfig
options for specifying the DMA configuration (channel, DMA device name)
with getting that from devicetree.  We also get pincfg from devicetree,
however we still have Kconfig sybmols to specify if the RF or RK pin is
enabled.

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2020-05-07 22:24:58 -05:00
Kumar Gala
cb8ee73692 dts: atmel sam: Add pinctrl support for SAM SPI
Add pinctl support for the SAM SPI device.  We update the SPI
binding to have pinctrl-0 bindings that are expected to have
at least phandles for MISO, MOSI, and SPCK, but might also have
various chip selects as well.

The pinctrl nodes will have an 'atmel,pins' property that describes the
GPIO port, pin and periphal configuration for that pin.

We update sam*-pinctrl.dtsi files with all the various pin ctrl
configuration operations supported by the given SoC family.  These
files are based on data extracted from the Atmel ASF HAL
(in include/sam<FAMILY>/pio/*.h).

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2020-04-25 09:29:54 -05:00
Kumar Gala
1b0e4124da dts: atmel sam: Add pinctrl support for SAM TWI and TWIHS I2C
Add pinctl support for the SAM TWI and TWIHS I2C devices.  We update
the TWI and TWIHS I2C bindings to have pinctrl-0 bindings that are
expected to have 2 phandles to the TWCK & TWD pinctrl nodes.

The pinctrl nodes will have an 'atmel,pins' property that describes the
GPIO port, pin and periphal configuration for that pin.

We update sam*-pinctrl.dtsi files with all the various pin ctrl
configuration operations supported by the given SoC family.  These
files are based on data extracted from the Atmel ASF HAL
(in include/sam<FAMILY>/pio/*.h).

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2020-04-21 15:46:30 -05:00
Kumar Gala
bdf58d11f0 dts: atmel sam: Add pinctrl support for SAM UART and USART
Add pinctl support for the SAM UART and SAM USART devices.  We update
the UART and USART bindings to have pinctrl-0 bindings that are expected
to have 2 phandles to the RX & TX pinctrl nodes.

The pinctrl nodes will have an 'atmel,pins' property that describes the
GPIO port, pin and periphal configuration for that pin.

We add sam*-pinctrl.dtsi files with all the various pin ctrl
configuration operations supported by the given SoC family.  These
files are based on data extracted from the Atmel ASF HAL
(in include/sam<FAMILY>/pio/*.h).

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2020-04-18 17:04:08 -05:00