Remove leading/trailing blank lines in .c, .h, .py, .rst, .yml, and
.yaml files.
Will avoid failures with the new CI test in
https://github.com/zephyrproject-rtos/ci-tools/pull/112, though it only
checks changed files.
Move the 'target-notes' target in boards/xtensa/odroid_go/doc/index.rst
to get rid of the trailing blank line there. It was probably misplaced.
Signed-off-by: Ulf Magnusson <Ulf.Magnusson@nordicsemi.no>
simcall must be in the volatile asm so that gcc does not optimize it
out. It also needs "memory" clobber to make sure data passed through
memory buffer is actually written back before the simcall.
Change-Id: I410b7348bf605d0d08f81ec5395f6cb144f33a43
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
