This change addresses issue# 21756 where the expected thread
count does not match because kscan module is enabled in this board.
The Microchip kscan driver is contributing to the total thread count,
therefore interfering with the expected test result.
Signed-off-by: Francisco Munoz <francisco.munoz.ruiz@intel.com>
All board defconfig files currently set the architecture in addition to
the board and the SoC, by setting e.g. CONFIG_ARM=y. This spams up
defconfig files.
CONFIG_<arch> symbols currently being set in configuration files also
means that they are configurable (can be changed in menuconfig and in
configuration files), even though changing the architecture won't work,
since other things get set from -DBOARD=<board>. Many boards also allow
changing the architecture symbols independently from the SoC symbols,
which doesn't make sense.
Get rid of all assignments to CONFIG_<arch> symbols and clean up the
relationships between symbols and the configuration interface, like
this:
1. Remove the choice with the CONFIG_<arch> symbols in arch/Kconfig and
turn the CONFIG_<arch> symbols into invisible
(promptless/nonconfigurable) symbols instead.
Getting rid of the choice allows the symbols to be 'select'ed (choice
symbols don't support 'select').
2. Select the right CONFIG_<arch> symbol from the SOC_SERIES_* symbols.
This makes sense since you know the architecture if you know the SoC.
Put the select on the SOC_* symbol instead for boards that don't have
a SOC_SERIES_*.
3. Remove all assignments to CONFIG_<arch> symbols. The assignments
would generate errors now, since the symbols are promptless.
The change was done by grepping for assignments to CONFIG_<arch>
symbols, finding the SOC_SERIES_* (or SOC_*) symbol being set in the
same defconfig file, and putting a 'select' on it instead.
See
https://github.com/ulfalizer/zephyr/commits/hide-arch-syms-unsquashed
for a split-up version of this commit, which will make it easier to see
how stuff was done. This needs to go in as one commit though.
This change is safer than it might seem re. outstanding PRs, because any
assignment to CONFIG_<arch> symbols generates an error now, making
outdated stuff easy to catch.
Signed-off-by: Ulf Magnusson <Ulf.Magnusson@nordicsemi.no>
Configure as GPIOs pins that by default are not GPIOs
Enable pinmux for port F
Enable ADC, PWM drivers by default, but keep SPI disabled.
Swap I2C instances since I2C0 is multiplexed with UART2
Select VTR3 as 1.8V
Signed-off-by: Jose Alberto Meza <jose.a.meza.arellano@intel.com>
Created MEC1501 deep and light sleep example for MCHP MEC1501.
Modifications were made to SoC, board, timer, and hello world
sample program. Power management split into SoC power
implementing the interface and device power for device specific
logic.
Signed-off-by: Scott Worley <scott.worley@microchip.com>
Enable PS/2 instances in dts and mux data and clk pins.
It also contains new Kconfig switches for the PS/2 controller
Signed-off-by: Francisco Munoz <francisco.munoz.ruiz@intel.com>
MEC1501 RTOS timer internal counter is on the 32KHz clock domain.
The register interface is on the AHB clock. When the timer is started
hardware synchronizes to the next 32KHz clock edge resulting is a
variable delay moving the value in the preload register into the
count register. The maximum delay is one 32KHz clock period (30.5 us).
We work-around this delay by checking if the timer has been started
and not using the count value which is still 0. Instead we state zero
counts have elapsed.
Signed-off-by: Scott Worley <scott.worley@microchip.com>
Expose eSPI block with interrupts enabled for channel 0 & 1
eSPI handshake has been tested using espi driver sample app
Signed-off-by: Jose Alberto Meza <jose.a.meza.arellano@intel.com>
Add a kernel timer driver for the MEC1501 32KHz RTOS timer.
This timer is a count down 32-bit counter clocked at a fixed
32768 Hz. It features one-shot, auto-reload, and halt count down
while the Cortex-M is halted by JTAG/SWD. This driver is based
on the new Intel local APIC driver. The driver was tuned for
accuracy at small sleep values. Added a work-around for RTOS
timer restart issue. RTOS timer driver requires board ticks per
second to be 32768 if tickless operation is configured.
Signed-off-by: Scott Worley <scott.worley@microchip.com>
Use the generic pinmux APIs provided by zephyr to select
alternate functions.
This also contains a fix for a formatting issue in the
documentation for this board. Additionally, the serial
console is now on UART2.
Signed-off-by: Francisco Munoz <francisco.munoz.ruiz@intel.com>
This was tested with the hello world application. UART 0 was used
as console for displaying "Hello World! mec15xxevb_assy6853" to
the serial terminal.
Signed-off-by: Scott Worley <scott.worley@microchip.com>
soc : arm : microchip_mec Use rename fault clear function
The Cortex-M core function to clear faults was rename by
upstream. Update to use new name.
Signed-off-by: Scott Worley <scott.worley@microchip.com>
