Commit graph

1473 commits

Author SHA1 Message Date
Andrew Boie
7d7f4336c8 x86: don't default to 'y' for spectre configs
The SOC code can set whether it's known that the CPU
is immune, don't default to turning this off.

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2019-03-01 12:35:04 -08:00
Andrew Boie
d3c89fea4f kernel: move CONFIG_RETPOLINE definition
Retpolines were never completely implemented, even on x86.
Move this particular Kconfig to only concern itself with
the assembly code, and don't default it on ever since we
prefer SSBD instead.

We can restore the common kernel-wide CONFIG_RETPOLINE once
we have an end-to-end implementation.

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2019-03-01 12:35:04 -08:00
Andrew Boie
ad2d7ca081 x86: fix page directory out of bounds
PAE page tables (the only kind we support) have 512
entries per page directory, not 1024.

Fixes: #13838

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2019-02-28 15:03:06 -08:00
Andrew Boie
9a7355dfad x86: gen_idt.py: add docstring
Provide additional details on what this script does.

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2019-02-25 13:15:37 -08:00
Andrew Boie
e64d18b343 x86: gen_mmu_x86: add docstring and copyright
Provide additional details on what this script does.

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2019-02-25 13:15:37 -08:00
Andrew Boie
a77914c140 x86: gen_mmu_x86.py: simplify usage
We don't need the build system to pull out the mmu
region specifiers from the kernel binary when the
script can just as easily do this itself.

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2019-02-25 13:15:37 -08:00
Andrew Boie
b8cbf21990 x86: gen_gdt.py: expand doctsring
Provide more detail on what this script does.

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2019-02-25 13:15:37 -08:00
Andrew Boie
cfde940d6d x86: relocate some arch-specific scripts
These scripts are specific to the x86 port.

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2019-02-25 13:15:37 -08:00
Andrew Boie
4ce652e4b2 userspace: remove APP_SHARED_MEM Kconfig
This is an integral part of userspace and cannot be used
on its own. Fold into the main userspace configuration.

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2019-02-23 07:43:55 -05:00
Sebastian Bøe
b75115a49e cmake: Fix dependency issue in x86 build scripts
Incremental builds have been broken in x86 due to a misconfigured
dependency. mmu_tables.bin is always generated, even for "nothing to
do" builds.

We fix this by removing the stray dependency on user_mmu_tables.bin
when not CONFIG_X86_KPTI.

Steps to reproduce:

Build any sample twice with qemu_x86 and observe that the second build
regenerates mmu_tables.bin.

Signed-off-by: Sebastian Bøe <sebastian.boe@nordicsemi.no>
2019-02-20 14:09:59 -05:00
Sebastian Bøe
c330f32079 cmake: x86: Refactor build scripts
The same pattern is used five times In the x86 build scripts and the
same code has been copied and modified the same amount of times. This
has resulted in a system that is difficult to make changes to.

To enforce consistency and improve maintainability we refactor the
code into a function.

Signed-off-by: Sebastian Bøe <sebastian.boe@nordicsemi.no>
2019-02-19 10:00:14 -08:00
Sebastian Bøe
00b2e54b1c cmake: x86: Add wrapper targets for custom commands
In general, to have correct dependencies, one must not only depend on
files, but also a wrapper target for the file. This is done for some
of the files in arch/x86/CMakeLists.txt, but not all.

To be consistent with how dependency management is done we add wrapper
targets and add dependencies to them.

Signed-off-by: Sebastian Bøe <sebastian.boe@nordicsemi.no>
2019-02-19 10:00:14 -08:00
Sebastian Bøe
d515315a86 ld: Change the name of input section irq_vectors_alloc_data
The arch/x86/CMakeLists.txt build scripts names five sections that are
generated from .bin files. Two of them are named the same as the .bin
file, and the other three are named inconsistently.

To be consistent, we will rename the three that are named inconistenly
to align with the two that are named as the .bin file.

Being consistent simplifies the system and fosters code-reuse.

This patch renames irq_vectors_alloc_data.

Signed-off-by: Sebastian Bøe <sebastian.boe@nordicsemi.no>
2019-02-19 10:00:14 -08:00
Sebastian Bøe
c5837eabcb ld: Change the name of input section .gdt_ram_data to gdt
The arch/x86/CMakeLists.txt build scripts names five sections that are
generated from .bin files. Two of them are named the same as the .bin
file, and the other three are named inconsistently.

To be consistent, we will rename the three that are named inconistenly
to align with the two that are named as the .bin file.

Being consistent simplifies the system and fosters code-reuse.

This patch renames gdt.

Signed-off-by: Sebastian Bøe <sebastian.boe@nordicsemi.no>
2019-02-19 10:00:14 -08:00
Sebastian Bøe
d1a14b7eb2 ld: Change the name of section .user_mmu_data to user_mmu_tables
The arch/x86/CMakeLists.txt build scripts names five sections that are
generated from .bin files. Two of them are named the same as the .bin
file, and the other three are named inconsistently.

To be consistent, we will rename the three that are named inconistenly
to align with the two that are named as the .bin file.

Being consistent simplifies the system and fosters code-reuse.

This patch renames user_mmu_tables.

Signed-off-by: Sebastian Bøe <sebastian.boe@nordicsemi.no>
2019-02-19 10:00:14 -08:00
Sebastian Bøe
d5ea49bcbd ld: Change the name of input section .mmu_data to mmu_tables
The arch/x86/CMakeLists.txt build scripts names five sections that are
generated from .bin files. Two of them are named the same as the .bin
file, and the other three are named inconsistently.

To be consistent, we will rename the three that are named inconistenly
to align with the two that are named as the .bin file.

Being consistent simplifies the system and fosters code-reuse.

This patch renames mmu_tables.

Signed-off-by: Sebastian Bøe <sebastian.boe@nordicsemi.no>
2019-02-19 10:00:14 -08:00
Andrew Boie
5f4683db34 x86: fix ROM permissions
Only the text area now has execute permissions,
instead of both text and rodata.

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2019-02-15 13:10:18 -08:00
Andrew Boie
65da531aed x86: fix exception stack pointer reporting
If the faulting context is in user mode, then we are
not on the same stack due to HW-level stack switching
on privilege elevation, and the faulting ESP is on
the stack itself.

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2019-02-15 09:48:37 -05:00
Andrew Boie
21337019b0 x86: get oops reason code more robustly
The code did not consider privilege level stack switches.
We have the original stack pointer in the NANO_ESF,
just use that.

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2019-02-15 09:48:37 -05:00
Andrew Boie
747dcbc8f2 x86: improve stack overflow detection
We now have a dedicated function to test whether
a memory region is withing the boundary of the
faulting context's stack buffer.

We use this to determine whether a page or double fault
was due to ESP being outside the bounds of the stack,
as well as when unwinding stack frames to print debug
output.

Fixes two issues:
- Stack overflows in user mode being incorrectly reported
  as just page fault exceptions
- Exceptions that occur when unwinding corrupted stacks

The type of fault which triggered the stack overflow
logic (double or page fault) is now always shown.

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2019-02-15 09:48:37 -05:00
Andrew Boie
62d866385e x86: fix crash in _arch_buffer_validate
The code wasn't checking if the memory address to check
corresponded to a non-present page directory pointer
table entry.

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2019-02-14 12:46:36 -05:00
Andrew Boie
2cfeba8507 x86: implement interrupt stack trampoline
Upon hard/soft irq or exception entry/exit, handle transitions
off or onto the trampoline stack, which is the only stack that
can be used on the kernel side when the shadow page table
is active. We swap page tables when on this stack.

Adjustments to page tables are now as follows:

- Any adjustments for stack memory access now are always done
  to the user page tables

- Any adjustments for memory domains are now always done to
  the user page tables

- With KPTI, resetting a page now clears the present bit

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2019-02-14 12:46:36 -05:00
Andrew Boie
eea0f93a83 x86: generate user mode page tables
If kernel page table isolation is enabled, we generate a second
set of page tables. These tables, except for the shared page, have
all non-user pages marked as non-present.

The MMU generation script has been refactored:

- Debugging output has been make significantly simpler and less
  verbose

- Useless globals removed or adjusted

- MMU region list is validated as it is read

- Some tuples unpacked into individual variables to make the
  code easier to read.

- Useless command line option for output binary endian-ness
  remobved

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2019-02-14 12:46:36 -05:00
Andrew Boie
f093285345 x86: modify MMU APIs for multiple page tables
Current set of APIs and macros assumed that only one set
of page tables would ever be in use.

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2019-02-14 12:46:36 -05:00
Andrew Boie
89a127bc8e x86: add Kconfig for KPTI
This will be enabled by default for any x86 that isn't
noted as being immune to this CPU bug.

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2019-02-14 12:46:36 -05:00
Andrew Boie
d2886ab8bc x86: clear EFLAGS on double fault
In the event of a double fault, we do a HW task switch to
a special _df_tss hardware task which resets the stack
pointer to the interrupt stack and otherwise restores
the main hardware task to a runnable state so that
_df_handler_bottom() can run.

However, we need to make sure that _df_handler_bottom()
runs with interrupts locked, otherwise another IRQ could
corrupt the interrupt stack resulting in undefined
behavior.

We have very little stack space to work with in this
context, just zero it. It's a fatal error for the thread
in any event.

Fixes: #7291

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2019-02-13 10:58:42 -08:00
Piotr Zięcik
9cc63e07e4 power: Fix naming of Kconfig options controlling deep sleep states
This commit changes the names of SYS_POWER_DEEP_SLEEP* Kconfig
options in order to match SYS_POWER_LOW_POWER_STATE* naming
scheme.

Signed-off-by: Piotr Zięcik <piotr.ziecik@nordicsemi.no>
2019-02-12 07:46:32 -05:00
Andrew Boie
f087cd0774 x86: fix app_smem MMU permissions
At boot, user threads were being granted access to the entire
app shared memory section. This is incorrect; user threads should
have no access until they are added to a memory domain, which
may contain partitions defined within it.

Change from MMU_ENTRY_USER (which grants permission at boot)
to MMU_ENTRY_RUNTIME_USER (which indicates that the pages may
be granted to user mode at runtime, but not at boot).

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2019-02-08 14:02:31 -08:00
Andy Ross
aa6e21c24c kernel: Split _Swap() API into irqlock and spinlock variants
We want a _Swap() variant that can atomically release/restore a
spinlock state in addition to the legacy irqlock.  The function as it
was is now named "_Swap_irqlock()", while _Swap() now refers to a
spinlock and takes two arguments.  The former will be going away once
existing users (not that many!  Swap() is an internal API, and the
long port away from legacy irqlocking is going to be happening mostly
in drivers) are ported to spinlocks.

Obviously on uniprocessor setups, these produce identical code.  But
SMP requires that the correct API be used to maintain the global lock.

Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
2019-02-08 14:49:39 -05:00
Andrew Boie
41f6011c36 userspace: remove APPLICATION_MEMORY feature
This was never a long-term solution, more of a gross hack
to get test cases working until we could figure out a good
end-to-end solution for memory domains that generated
appropriate linker sections. Now that we have this with
the app shared memory feature, and have converted all tests
to remove it, delete this feature.

To date all userspace APIs have been tagged as 'experimental'
which sidesteps deprecation policies.

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2019-02-08 07:04:30 -05:00
Andrew Boie
71a3b53504 x86: don't automatically configure newlib malloc
This diverges from policy for all of our other arches
and C libraries. Global access to the malloc arena
may not be desirable.

Forthcoming patch will expose, for all C libraries, a
k_mem_partition with the malloc arena which can be
added to domains as desired.

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2019-02-08 07:04:30 -05:00
Adithya Baglody
9bebf4cb23 x86: fix app shared memory if XIP enabled
This is a separate data section which needs to be copied into
RAM.

Most arches just use the kernel's _data_copy(), but x86 has its
own optimized copying code.

Signed-off-by: Adithya Baglody <adithya.nagaraj.baglody@intel.com>
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2019-02-08 07:04:30 -05:00
Andrew Boie
2d9bbdf5f3 x86: remove support for non-PAE page tables
PAE tables introduce the NX bit which is very desirable
from a security perspetive, back in 1995.

PAE tables are larger, but we are not targeting x86 memory
protection for RAM constrained devices.

Remove the old style 32-bit tables to make the x86 port
easier to maintain.

Renamed some verbosely named data structures, and fixed
incorrect number of entries for the page directory
pointer table.

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2019-02-05 20:51:21 -08:00
Sebastian Bøe
1526070082 cmake: Use a variable for 'zephyr_prebuilt'
There is an effort underway to make most of the Zephyr build script's
reentrant. Meaning, the build scripts can be executed multiple times
during the same CMake invocation.

Reentrancy enables several use-cases, the motivating one is the
ability to build several Zephyr executables, or images, for instance a
bootloader and an application.

For build scripts to be reentrant they cannot be directly referencing
global variables, like target names, but must instead reference
variables, which can vary from entry to entry.

Therefore, in this patch, we replace global targets with variables.

Signed-off-by: Sebastian Bøe <sebastian.boe@nordicsemi.no>
2019-01-19 07:21:55 -05:00
Adithya Baglody
cb536111a9 Gcov: Added support for x86.
This patch adds all the required hooks needed in the kernel to
get the coverage reports from x86 SoCs.

Signed-off-by: Adithya Baglody <adithya.nagaraj.baglody@intel.com>
2019-01-16 06:12:33 -05:00
Flavio Ceolin
6d50df212f arch: x86: Make statements evaluate boolean expressions
MISRA-C requires that the if statement has essentially Boolean type.

MISRA-C rule 14.4

Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
2019-01-07 08:52:07 -05:00
Anas Nashif
74a74bb6b8 power: rename api sys_soc -> sys_
sys_soc is just redundant, just call APIs with sys_*.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2018-12-28 16:16:28 -05:00
Anas Nashif
9151fbebf2 power: rename APIs and removing leading _
Remove leading underscore from PM APIs. _ was used for internal APIs.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2018-12-28 16:16:28 -05:00
Sebastian Bøe
bdda09ee93 cmake: Remove dead code LTO references
LTO is not supported yet, but there are a handful of references to the
flag '-flto' and the non-existent Kconfig option 'LTO'. To not confuse
users about whether LTO is supported or not, we should remove this
dead code.

As an aside, prototyping has shown that supporting LTO will give
signicant (10%) code size improvments, but will not be trivial to
support due to how we process object files with python.

Signed-off-by: Sebastian Bøe <sebastian.boe@nordicsemi.no>
2018-12-21 21:04:18 +01:00
Flavio Ceolin
0ed0d164ef arch: x86: Use macro BIT to shift bits
The operation was shifiting bit using a signed constant in the left
operand. Use BIT macro to do it properly.

MISRA-C rule 12.2

Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
2018-12-11 14:37:10 -08:00
Flavio Ceolin
4b35dd2628 misra: Fixes for MISRA-C rule 8.2
In C90 was introduced function prototype, that allows argument types
to be checked against parameter types, though it is not necessary
specify names for the parameters. MISRA-C requires names for function
prototype parameters, it claims that names can provide useful
information regarding the function interface.

MISRA-C rule 8.2

Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
2018-12-07 09:06:34 -05:00
Flavio Ceolin
34b12d8f16 arch: x86: x86_mmu: Remove possible dead code
When __ASSERT is not enabled there is an attribution to the variable
total_partitions and it is never used.

MISRA-C rule 2.2

Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
2018-12-07 09:06:34 -05:00
Flavio Ceolin
1492df3415 x86: core: thread: Avoid clash with function identifier
There is a function called _thread_entry defined in
lib/thread_entry.c. Just changing name to fix MISRA-C violation.

MISRA-C rule 5.8

Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
2018-12-07 09:06:34 -05:00
Flavio Ceolin
c42dc9435d arch: x86: Make tag name unique
Renaming a variable to not clash with a struct name.

MISRA-C rule 5.7

Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
2018-12-07 09:06:34 -05:00
Andrew Boie
ab82ef4ca5 x86: always build the page fault handler
Previously, this was only built if CONFIG_EXCEPTION_DEBUG
was enabled, but CONFIG_USERSPACE needs it too for validating
strings sent in from user mode.

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2018-12-06 12:44:23 -08:00
Andrew Boie
d4363e4185 x86: print helpful message on FPU exception
A few people have tripped over this recently.

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2018-12-06 12:44:23 -08:00
Ioannis Glaropoulos
39bf24a9bd kernel: expose k_mem_partition_attr_t outside User mode
This commit exposes k_mem_partition_attr_t outside User Mode, so
we can use struct k_mem_partition for defining memory partitions
outside the scope of user space (for example, to describe thread
stack guards or no-cacheable MPU regions). A requirement is that
the Zephyr build supports Memory protection. To signify this, a
new hidden, all-architecture Kconfig symbol is defined (MPU). In
the wake of exposing k_mem_partition_attr_t, the commit exposes
the MPU architecture-specific access permission attribute macros
outside the User space context (for all ARCHs), so they can be
used in a more generic way.

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2018-12-05 15:15:07 -05:00
Patrik Flykt
494ef1cfe2 arch: Add 'U' to unsigned variable assignments
Add 'U' to a value when assigning it to an unsigned variable.
MISRA-C rule 7.2

Signed-off-by: Patrik Flykt <patrik.flykt@intel.com>
2018-12-04 22:51:56 -05:00
Flavio Ceolin
6e1f6e5d5d arch: x86: Make if statement evaluate a boolean expression
MISRA-C rule 14.4

Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
2018-11-30 08:05:11 -08:00
Flavio Ceolin
001ad8b6c2 arch: Making body of selection statement a compound statement
MISRA-C rule 15.6

Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
2018-11-29 14:21:29 -08:00