michaelh/zephyr
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Author SHA1 Message Date
Fin Maaß
869845d6ab aesc: riscv: use riscv,isa-extensions dt prop 
use riscv,isa-extensions dt prop for riscv cpus.

Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
 2026-01-26 14:15:18 +01:00
Fin Maaß
514258aa23 riscv: select ATOMIC_OPERATIONS based on RISCV_ISA_EXT_A 
use RISCV_ISA_EXT_A to select ATOMIC_OPERATIONS_BUILTIN or
ATOMIC_OPERATIONS_C.

Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
 2025-06-30 15:17:47 -05:00
Daniel Schultz
3112f856d2 soc: Add aesc 
Currently, the only available platform is Nitrogen, featuring a
VexRiscv CPU that boots from external SPI flash and runs code from
external HyperRAM.

Signed-off-by: Daniel Schultz <dnltz@aesc-silicon.de>
 2025-05-14 14:09:41 +02:00