One of the ARM architure files, defined since long ago
CONCAT having the exact same purpose as Zephyr's _CONCAT.
Unfortunately this header is included almost always
and the macro defined in all ARM based platforms,
which seems to have lead to many uses of this macro
instead of _CONCAT.
Fix it by using _CONCAT instead.
Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
This new API returns the version string corresponding to a given
HCI version.
The API can be used by applications to print out human-readable
information about the controller being used.
Adding this API removes possible code duplication.
Signed-off-by: Rubin Gerritsen <rubin.gerritsen@nordicsemi.no>
Identifiers starting with an underscore and a capital letter
are reserved by the C standard.
Prefix '_POLL_EVENT' with an additional 'DECL' for better recognition.
Signed-off-by: Roman Kellner <rkellner@baumer.com>
When _POLL_EVENT becomes an empty define due to CONFIG_POLL,
it will create an empty line terminated with a semicolon.
Empty struct members contradict the C specification
eventhough most compiler will tolerate it without
-Wpedantic.
Signed-off-by: Roman Kellner <rkellner@baumer.com>
add support for card interrupt sources to SDHC drivers. This can be used
for SDIO card interrupts, or to detect card insertion/removal.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Extends the concept of halting a thread from just aborting a thread
to both aborting and suspending a thread.
Part of this involves updating k_thread_suspend() to operate in a
similar fashion to that of k_thread_abort().
Signed-off-by: Peter Mitsis <peter.mitsis@intel.com>
The halt queue will be used to identify threads that are waiting
for a thread on another CPU to finish suspending.
Signed-off-by: Peter Mitsis <peter.mitsis@intel.com>
This commit introduces SMP support into Cortex-A/R aarch32 architecture.
For now, this only supports multiple core start together and only allow
one CPU initialize system as primary core, others loop at the beginning
as the secondary cores and wait for wake up.
Signed-off-by: Huifeng Zhang <Huifeng.Zhang@arm.com>
This commit introduce 'USE_SWITCH' feature into cortex-A/R(aarch32)
architecture
For introducing USE_SWITCH, the exception entry and exit are unified via
`z_arm_cortex_ar_enter_exc` and `z_arm_cortex_ar_exit_exc`. All
exceptions including ISR are using this way to enter and exit exception
handler.
Differentiate exception depth and interrupt depth. Allow doing
context switch when exception depth greater than 1 but not allow doing
this when interrupt depth greater than 1.
Currently, USE_SWITCH doesn't support FPU_SHARING and USERSPACE.
Signed-off-by: Huifeng Zhang <Huifeng.Zhang@arm.com>
Store the current CPU's struct _cpu instance into TPIDRURO, so that the
CPU core can get its struct _cpu instance by reading TPIDRURO. This is
useful in the SMP system.
Signed-off-by: Huifeng Zhang <Huifeng.Zhang@arm.com>
For most types, ACPICA provides both a struct name as well as a typedef.
The struct names follow the exact same naming style as Zephyr's ACPI
API, which makes it impossible to distinguish which type is defined by
Zephyr and which comes from ACPICA. It's therefore better to use the
typedefs, since they follow a distinct style compared to the Zephyr API.
Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
The acpi_get_irq_routing_table() takes a pointer to an array of
ACPI_PCI_ROUTING_TABLE elements rather than a generic buffer pointer
(e.g. void *).
Because of the above, it makes sense to specify the array size as an
actual ARRAY_SIZE() value, since it makes no sense to accept buffers
which are not a multiple of sizeof(ACPI_PCI_ROUTING_TABLE) long.
Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
HCR_EL2 is configured to certain value by some
loaders such as Uboot on some arm64 boards(such as roc_rk3568_pc),
When HCR_EL2.TGE, HCR_EL2.AMO and HCR_EL2.IMO bits are
set to 1, some unpredictable behaviors may occur during
zephyr boot. So we clear these bits to avoid it.
Signed-off-by: Charlie Xiong <1981639884@qq.com>
Basic spinlock implementation is based on single
atomic variable and doesn't guarantee locking fairness
across multiple CPUs. It's even possible that single CPU
will win the contention every time which will result
in a live-lock.
Ticket spinlocks provide a FIFO order of lock aquisition
which resolves such unfairness issue at the cost of slightly
increased memory footprint.
Signed-off-by: Alexander Razinkov <alexander.razinkov@syntacore.com>
Add a note to all internal APIs signifying they are internal and should
not be used outside of the zephyr code base.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
