Changing pcie0 to pcie0: pcie0 allows it to be referenced as &pcie0. I
am not sure why this is required. Otherwise I get error:
...
parse error: undefined node label 'pcie0'
...
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Use the new PCIe core infrastructure for looking up the BDF at runtime
based on the VID/DID values.
Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
Use the new PCIe core infrastructure for looking up the BDF at runtime
based on the VID/DID values.
Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
Platforms that enable UART_NS16550_ACCESS_IOPORT (the case for ia32)
require reg-shift to be zero. Fix this issue introduced in
4c8a8149de.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
The ns16550 flags reg-shift property as optional. In case it is not
supplied, the ns16550 driver relies on a value defined in <soc.h>, or,
by default it takes 4 (shift by 2).
This patch adds the property to all ns16550 nodes, with the following
values:
- 2 if SoC did not have any custom value defined by
UART_REG_ADDR_INTERVAL (corresponds to 1 << 2 = 4)
- If SoC defined DEFAULT_REG_INTERVAL (snps_arc_iot/it8xxx2), use such
value (4=2, 2=1, 1=0).
These changes will allow simplifying the ns16550 driver.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
