If CONFIG_SPI_STATS is enabled, the device state for all SPI controller
drivers must contain the SPI stats. This space is allocated by calling
Z_SPI_INIT_FN as part of the device definition; this is done automatically
when using SPI_DEVICE_DT_DEFINE instead of DEVICE_DT_DEFINE. If space for
statistics is not properly allocated but CONFIG_SPI_STATS is enabled, an
unexpected write to memory outside of the stats region may occur on a SPI
transfer. This commit uses SPI_DEVICE_DT_DEFINE or
SPI_DEVICE_DT_INST_DEFINE for all in-tree SPI controller drivers.
Signed-off-by: Dane Wagner <dane.wagner@gmail.com>
Fix a build error when CONFIG_SPI_ASYNC is set.
The issue was detected by CI
```
spi_xlnx_axi_quadspi.c: In function 'xlnx_quadspi_isr':
spi_xlnx_axi_quadspi.c:489:21: error: 'ctx' undeclared
489 | if (ctx->asynchronous) {
| ^~~
```
Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
This driver could end up doing a great deal of work inside the ISR when
large SPI transfers were in use, which could cause significant IRQ
latency. For the normal, non-async SPI transfer case, use events to
signal the calling thread to complete the work rather than performing
FIFO transfers inside the ISR.
Signed-off-by: Robert Hancock <robert.hancock@calian.com>
Add an optional DT property to specify the size of the RX/TX FIFO
implemented within the SPI core. The property name used is the same one
used by Xilinx's device tree generator.
When the FIFO is known to exist, we can use the RX FIFO occupancy register
to determine how many words can be read from the RX FIFO without checking
the RX FIFO empty flag after every read. Likewise with the TX FIFO, we can
use the FIFO size to avoid checking the FIFO full flag after every write.
This can increase overall throughput.
Signed-off-by: Robert Hancock <robert.hancock@calian.com>
Add support for a workaround required when using the Xilinx Quad SPI core
with the USE_STARTUP option, which routes the core's SPI clock to the
FPGA's dedicated CCLK pin rather than a normal I/O pin. This is typically
used when interfacing with the same SPI flash device used for FPGA
configuration. In this mode, the SPI core cannot actually take control
of the CCLK pin until a few clock cycles are issued, which would break
the first transfer issued by the core. This workaround applies a dummy
command to the connected device to ensure that the clock signal is in the
correct state for subsequent commands.
See Xilinx answer record at:
https://support.xilinx.com/s/article/52626?language=en_US
Signed-off-by: Robert Hancock <robert.hancock@calian.com>
Change automated searching for files using "IRQ_CONNECT()" API not
including <zephyr/irq.h>.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Adds a new spi_transcieve_cb API which enables asynchronous
SPI transactions with callback notification.
The exist spi_transcieve_async API remains and uses the new
spi_transcieve_cb API to provide a k_poll_signal notifier.
The driver API changes to provide a callback and userdata
parameter to async transcieve. All drivers in the tree
have been updated to the change.
Signed-off-by: Tom Burdick <thomas.burdick@intel.com>
In order to bring consistency in-tree, migrate all drivers to the new
prefix <zephyr/...>. Note that the conversion has been scripted, refer
to #45388 for more details.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
In case when we have multiple devices connected to the
one SPI interface the initial state of CS gpios after
MCU reset is floating and it might be low that prevents us from
communicating between particular devices. Fix that by
initializing all provided cs gpios and setting them as inactive.
Signed-off-by: Bartosz Bilas <bartosz.bilas@hotmail.com>
A couple of SPI drivers use CONFIG_KERNEL_INIT_PRIORITY_DEVICE
as init priority for driver initialization. Let's change
it to the dedicated CONFIG_SPI_INIT_PRIORITY to make it
compatible with other ones.
Signed-off-by: Bartosz Bilas <bartosz.bilas@hotmail.com>
Keep locking for SPI_LOCK_ON from the first call of transceive until
spi_release release the lock. Use owner parameter to in the spi_context
to store the owner of the lock.
The locking is in line with the SPI_HOLD_ON_CS
Signed-off-by: Stefan Bigler <stefan@bigler.io>
These are all the case that coccinelle cannot find as they are inside
macro declarations.
Fixed via:
git grep -rlz -E "\(struct device \*" |
xargs -0 sed -i 's/(struct device/(const struct device/g'
Fixes#27399
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
Now that device_api attribute is unmodified at runtime, as well as all
the other attributes, it is possible to switch all device driver
instance to be constant.
A coccinelle rule is used for this:
@r_const_dev_1
disable optional_qualifier
@
@@
-struct device *
+const struct device *
@r_const_dev_2
disable optional_qualifier
@
@@
-struct device * const
+const struct device *
Fixes#27399
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
Add SPI driver for the Xilinx AXI Quad SPI IP. Despite the name, this IP
block supports both single, dual, and quad line widths.
Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
