Introduce an interactive multi-vector steering redirection table
probe subcommand to the common PCIe host shell driver layer.
The IRQ subsystem extracts MSI-X registers using pcie_get_cap()
offsets, decoding allocated vector pools and exposing steering
offsets via standard Base Address Register (BAR) bitmasks.
Signed-off-by: Khadem Ullah <khadem.systems@gmail.com>
Introduce a dynamic hardware capability offload telemetry probe
command to the common PCIe host shell subsystem layer.
The capability subsystem automatically resolves and decodes the
Device Capabilities 2 (DEVCAP2) register map via the native
pcie_get_cap() engine. It evaluates bitmasks for Alternative
Routing-ID (ARI) and Single-Root I/O Virtualization (SR-IOV).
Signed-off-by: Khadem Ullah <khadem.systems@gmail.com>
Implement the 'pcie link speed <bus:dev.func>' shell subcommand to allow
runtime discovery, interrogation, and bitfield decoding of the PCI Express
Link Capabilities and Link Status capability registers (Cap ID 0x10).
Signed-off-by: Khadem Ullah <khadem.systems@gmail.com>
Implement the 'pcie device state <bus:dev.func> up|down' shell
subcommand to allow runtime interrogation, status tracking, and
bit-level state mutation of the standard PCI Power Management
Capability block (Cap ID 0x01).
The command scans the traditional capability linked list within
traditional configuration space to locate the power block base offset.
It utilizes a read-modify-write routine targeting the Power Management
Control/Status Register (PMCSR) to transition the underlying hardware
transceiver between the D0 Fully Operational state (00b) and the
D3hot Low Energy Suspend state (11b).
Signed-off-by: Khadem Ullah <khadem.systems@gmail.com>
Implement the 'pcie link margin <bus:dev.func>' shell subcommand to
allow runtime discovery, interrogation, and bitfield decoding of the
PCI Express Lane Margining at Receiver extended capability structures
(Extended Cap ID 0x001A).
The command dynamically traverses the PCIe Extended Configuration Space
(offsets >= 0x100) to isolate the margining block base. It reads the
underlying hardware registers and unpacks the 16-bit Port Capabilities
and Control fields to report maximum voltage/timing steps, total link
widths, and independent per-lane software execution controls. It also
polls active receiver signal status flags and bounds tracking limit
thresholds.
Signed-off-by: Khadem Ullah <khadem.systems@gmail.com>
Implement the 'pcie aer status <bus:dev.func>' shell subcommand to allow
runtime interrogation and decoding of the PCI Express Advanced Error
Reporting (AER) capability registers.
The command handles hardware traversal across the PCIe Extended Capability
Space (offsets >= 0x100) to dynamically isolate the AER capability block
and read configuration space registers. It decodes uncorrectable fatal
and non-fatal register flags—including Link Training errors, Data Link
Protocol errors, Poisoned TLPs, and Flow Control Protocol breakdown states—
as well as correctable signal layer degradation deviations.
Signed-off-by: Khadem Ullah <khadem.systems@gmail.com>
This patch introduces a `pcie irq status` sub-command to the common
PCIe host shell subsystem layer.
The utility decodes legacy INTx pin and line metrics, structures real-time
traversals across standard device capabilities loops, and maps standard
MSI (Cap ID 0x05) and MSI-X (Cap ID 0x11) status parameters. The resulting
trace logs track active configuration states, vector capabilities, target
message address fields, and MSI-X table sizing dimensions to simplify
embedded hardware interrupt triage tasks.
Signed-off-by: Khadem Ullah <khadem.systems@gmail.com>
This patch introduces a `pcie link set_speed` sub-command utility
to the PCIe host shell subsystem layer.
The tool locates the native PCI Express Capability structure (Cap ID
0x10), updates the Target Link Speed bitfield inside the Link Control
2 register, and issues a Retrain Link command override to the physical
layer. This enables developers to interactively scale bus power and
performance profiles directly from the command line window.
Signed-off-by: Khadem Ullah <khadem.systems@gmail.com>
This patch introduces a standalone root-level shell command utility
named `pcie_resource` to decode and evaluate PCIe Base Address Register
(BAR) spaces dynamically from the serial console interface.
The command operates within its own dedicated top-level namespace to
prevent redefinition conflicts with existing shell subsystem tables. It
iterates through standard configuration offsets (BAR0 to BAR5), executes
the standard PCI write-all-1s probing algorithm to calculate resource
footprints, and decodes aperture characteristics natively. The output
provides human-readable size geometry metrics, 32-bit vs. 64-bit bounds,
prefetchable memory attributes, and I/O port address space layouts.
Signed-off-by: Khadem Ullah <khadem.systems@gmail.com>
Introduce a dynamic software-based masking registry table to
the common PCIe host subsystem layer via the shell.
The masking subsystem features an explicit hook callback pointer that can
be runtime-registered via dynamic terminal command invocations. When
active, the core `scan_dev` device bus enumerator intercepts the BDF
coordinate before running the physical hardware registers discovery
sweeps. If a target slot matches a registered ignore block, it is
gracefully bypassed.
Signed-off-by: Khadem Ullah <khadem.systems@gmail.com>
This patch introduces an interactive `pcie write` sub-command to
the native PCIe kernel shell subsystem layer.
The utility accepts string arguments from the terminal prompt,
checks for link responsiveness via PCIE_CONF_ID to prevent
unmapped interconnect bus lockups, and invokes the low-level
`pcie_conf_write` function directly over the target configuration
space index parameters. An immediate read-back verification
check is executed to confirm latch status stability.
Signed-off-by: Khadem Ullah <khadem.systems@gmail.com>
Type-1 enumeration left prefetchable memory as TODO, so 64-bit BARs
behind a PCI-to-PCI bridge were not forwarded. Program prefetch
base/limit (and upper 32 bits) like the existing non-prefetch MEM
window.
Also advance the ECAM allocation offset when region_get_allocate_base()
aligns a Type-1 window, so subsequent BAR allocations start at the
aligned base instead of overlapping the unaligned remainder.
Signed-off-by: Li Wan <wanli@kylinos.cn>
This patch introduces strict __ASSERT parameter validation gates to
the primary configuration read and write handlers within the ECAM
host bridge controller driver.
On platforms mapping multi-bus topologies, passing an out-of-bounds
bus index variable can cause a bit-field overflow and boundary
spillage, shifting overflow bits into upper address coordinates. The
driver then executes memory transactions over unallocated regions
inside the ECAM window, causing the hardware to return dummy data
blocks (0xFFFFFFFF) or leak address spaces silently.
Checking the raw bits before any bitwise shifts or extraction macros
are applied halts out-of-bounds parameter execution at the lowest
hardware choke point without interfering with multi-bus hierarchies
conforming to the PCI Express Specification.
Signed-off-by: Khadem Ullah <khadem.systems@gmail.com>
Enable the iProc endpoint driver by default when the corresponding
devicetree node is present.
Drop the now-redundant board defconfig selections from the bcm958402m2
variants.
Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@gmail.com>
ADd `brcm,iproc-pcie-ep-v2` to represent the version difference
with `brcm,iproc-pcie-ep`.
This property can replace the CONFIG_PCIE_EP_IPROC_V2.
So, we removed it.
Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@gmail.com>
Add support for scanning PCIe buses beyond bus 0 using a devicetree
property. Some platforms have PCIe devices on
non-zero buses that are not reachable through bridge
enumeration from bus 0.
Signed-off-by: Bindu S <bindu.s@intel.com>
When CONFIG_PCIE_CONTROLLER is enabled,
the chosen zephyr,pcie-controller also needs to
be enabled.
Also on platforms where this chosen is set the
pcie controller is needed for the pcie to work,
therefor enable it by default.
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
Use the "zephyr-keep-sorted-start/stop" comment to have CI check
the alphabetical order of includes, to help reducing the chance
of conflicts while contributing drivers.
Signed-off-by: Josuah Demangeon <me@josuah.net>
Use the device in register accesses. This allows to use this code with
multiple controllers instead of only the "chosen" one.
Signed-off-by: Christian Mauderer <christian.mauderer@embedded-brains.de>
This renames z_phys_map() and z_phys_unmap() to
k_mem_map_phys_bare() and k_mem_unmap_phys_bare()
respectively. This is part of the series to move memory
management functions away from the z_ namespace.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Move reading PCIE_CONF_CMDSTAT before actual usage. There are four
return branches before value is used.
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
I/O or memory decoding should be disabled via the command register
before sizing BAR for calculation MMIO size
Signed-off-by: Najumon B.A <najumon.ba@intel.com>
Do not enable subsystem/driver shell modules by default and stop abusing
CONFIG_SHELL_MINIMAL, which is internal to the shell subsystem, to decide
when to enable a driver shell.
The list of shell modules has grown considerably through the
years. Enabling CONFIG_SHELL for doing e.g. an interactive debug session
leads to a large number of shell modules also being enabled unless
explicitly disabled, which again leads to non-negligible increases in
RAM/ROM usage.
This commit attempts to establish a policy of subsystem/driver shell
modules being disabled by default, requiring the user/application to
explicitly enable only those needed.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
This moves the k_* memory management functions from sys/ into
kernel/ includes, as there are kernel public APIs. The z_*
functions are further separated into the kernel internal
header directory.
Also made a quick change to doxygen to group sys_mem_* into
the OS Memory Management group so they will appear in doc.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
This puts a ifdef guard around the inclusion of ACPICA header
file. The ACPICA module is not active unless CONFIG_ACPI is
also enabled so we should not be using that header without
CONFIG_ACPI also being enabled.
This was discovered by Coverity.
Fixes#60484
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
PCIe devices refer to interrupt nodes, but are initialized with the same
priority, making the sequence depending on the linking order. Add a new
symbol and set it to one unit after intc to ensure that the
initialization sequence is stable.
Found with:
west build -p -b qemu_cortex_a53 \
samples/drivers/virtualization/ivshmem/doorbell \
-DCONFIG_CHECK_INIT_PRIORITIES=y
...
ERROR: /soc/pcie@4010000000 PRE_KERNEL_1 40 <
/soc/interrupt-controller@8000000/its@8080000 POST_KERNEL 40
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
Note that only the the hardware round robin port arbitration capability
is being used.
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
Basic support of VC capability, where a driver can enable VC and map its
traffic classes.
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
This help to decipher PCIe capabilities supported by each listed device.
Shown only on a selected device and not on the general list.
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
