The HAL's FLEXSPI_TransferBlocking() now adds the sizes of all
preceding ports (from FLSHCR0) to the transfer's device address.
memc_flexspi_transfer() also adds the sizes of preceding ports, so the
offset was applied twice for any device not on port A1.
On FRDM-RW612 this makes the APS6404L PSRAM on port B1 fail to
initialize: the IP command is issued at 0x08000000 (64 MB + 64 MB)
instead of 0x04000000, which is outside the 72 MB FlexSPI address
space, the controller rejects it, and the driver returns -EIO
("Device aps6404l@2 is not ready"). Devices on port A1 are unaffected
since their offset is zero.
Only adjust the LUT sequence index here and let the HAL handle the
port address offset.
The HAL commit introducing the change is
757668aae79c80bf6ab92e744afaeb97f4c51700.
The manifest commit for the HAL is
b8c0ad5951.
Assisted-by: Claude:claude-opus-5
Signed-off-by: Camille BAUD <mail@massdriver.space>
(SRAMC), the external asynchronous parallel SRAM interface found on i.MX
RT118x SoCs (e.g. MIMXRT1189). At init the driver reads the async-SRAM
bus timing from devicetree, so the external SRAM becomes accessible as
a memory-mapped region. No runtime data-transfer API is implemented.
The SRAMCR0/SRAMCR1 timing registers reside in the BLK_CTRL_WAKEUPMIX
block; each populated chip-select is described as a sram child node.
Signed-off-by: Yongxu Wang <yongxu.wang@nxp.com>
Typically Zephyr device tree macros that take a node_id as argument
start with DT_ and those that take an inst start with DT_INST_.
For the STM32 clock driver we currently have two macros named
STM32_DT_INST_CLOCK_INFO_BY_NAME and STM32_CLOCK_INFO_BY_NAME.
For consistency, the latter is renamed STM32_DT_CLOCK_INFO_BY_NAME.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
On newer STM32 families (STM32U5, STM32H5, STM32N6, STM32MP1, STM32MP2,
STM32L5, STM32G4), the Flexible Memory Controller (FMC) features a
2-bit DATAHLD[1:0] field in FMC_BTRx and FMC_BWTRx registers to
configure data-hold cycles for asynchronous read and write accesses.
Currently, memc_stm32_nor_psram.c skips initializing .DataHoldTime in
both normal and extended timing configurations, forcing the field to
0 cycles and causing timing violations on external devices requiring
non-zero data hold duration (such as parallel display controllers).
Older FMC v1 controllers (STM32F4, STM32F7, STM32H7) lack DATAHLD
bits entirely and their HAL timing structs omit the DataHoldTime
member.
Add optional Devicetree properties st,data-hold-cycles and
st,data-hold-cycles-ext to st,stm32-fmc-nor-psram binding without a
YAML default to prevent generating existence flags on unsupported
targets.
In memc_stm32_nor_psram.c, conditionally populate DataHoldTime when
FMC_BTRx_DATAHLD_Pos or FMC_BTR1_DATAHLD_Pos is defined, and add
compile-time assertions to prevent misconfiguration on legacy SoCs.
Fixes#118296
Signed-off-by: Priyanshu Singh <singhpriyanshu9838@gmail.com>
This commit enables the new clock managers by switching the device
tree to use the new bindings. It also moves some initialization code
from the old clock manager to soc_early_init_hook() since some clocks
configuration needs to be done before the clock drivers are initialized.
Signed-off-by: Martin Hoff <martin.hoff@silabs.com>
Add memc_xspi_reset(): an XSPI software reset that invalidates the
controller's AHB read/prefetch buffer while keeping the LUT and device
config. The flash driver calls it after a program or erase so a
memory-mapped read issued right afterwards returns the freshly written
data instead of stale prefetched data.
Signed-off-by: Ruijia Wang <ruijia.wang@nxp.com>
MEMC_MCUX_XSPI was gated on DT_HAS_NXP_XSPI_PSRAM_ENABLED, but
FLASH_MCUX_XSPI selects it based only on DT_HAS_NXP_XSPI_NOR_ENABLED,
causing a Kconfig error on boards with XSPI NOR flash but no XSPI
PSRAM device. Move it to its own DT_HAS_NXP_XSPI_ENABLED block,
matching the existing MEMC_MCUX_FLEXSPI pattern.
Signed-off-by: Ruijia Wang <ruijia.wang@nxp.com>
The SiWG917 has a data cache in front of PSRAM (family reference manual
rev 1.2 section 5.4.5). The bootloader leaves it enabled and nothing in a
Zephyr build maintains it: the SoC does not select CPU_HAS_DCACHE and
sys_cache_data_*() return -ENOTSUP. The network processor writes the same
memory, so contents read back stale or torn under load.
Disable it with the vendor call at the top of the memory controller init,
before PSRAM is set up.
Signed-off-by: Mikey Sklar <mikeysklar@gmail.com>
The FlexSPI controller configuration (LUT, per-device FLSHCR/DLLCR)
is lost when the controller power domain is powered down. On
PM_DEVICE_ACTION_TURN_ON, reset the memc per-port LUT bookkeeping so
the probe re-allocates LUT slots from zero, then re-run the flash
probe to rebuild the device configuration and LUT from the chip.
Re-running the controller init or wiping the whole LUT is not
possible while the CPU executes XIP from the NOR, so the restore
relies on the ROM FCB controller-level state and replaces (not
clears) the LUT entries the driver owns.
Add memc_flexspi_reset_lut_alloc() to reset the per-port LUT
bookkeeping after a power-domain power-down.
Signed-off-by: Albort Xue <yao.xue@nxp.com>
The current driver is prepared for the SAM4 which has a
8-bit interface only. This commit adds optional config
to support also 16-bit interfaces for the SAME7 family.
Signed-off-by: Sven Ginka <s.ginka@sensry.de>
Co-authored-by: Pieter De Gendt <pieter.degendt@gmail.com>
Replace the hardcoded MSPI_XFER_LITTLE_ENDIAN value in
MSPI_DEVICE_CONFIG_INIT() with DT_ENUM_IDX_OR(), so the
init_cfg endian field is driven by the mspi-endian property
of the device node when present, falling back to big-endian
when the property is absent.
Signed-off-by: Dhanoo Surasarang <dhanoo.surasarang@nordicsemi.no>
XIP in Zephyr is a software configuration concept (CONFIG_XIP). The MSPI
feature gated by MSPI_XIP only memory-maps the device into the SoC
address space; the mapped region can be used for plain data access as
well as code execution. Rename the feature to MEMMAP to reflect what it
actually does:
- CONFIG_MSPI_XIP -> CONFIG_MSPI_MEMMAP
- CONFIG_FLASH_MSPI_XIP_READ -> CONFIG_FLASH_MSPI_MEMMAP_READ
- struct mspi_xip_cfg -> struct mspi_memmap_cfg
- enum mspi_xip_permit / MSPI_XIP_READ_* -> mspi_memmap_permit /
MSPI_MEMMAP_READ_*
- mspi_xip_config() -> mspi_memmap_config(), driver API entry
xip_config -> memmap_config
- MSPI_XIP_CONFIG_DT{,_INST,_NO_CHECK} -> MSPI_MEMMAP_CONFIG_DT{,...}
- MSPI_XIP_CFG_STRUCT_DECLARE / MSPI_XIP_BASE_ADDR_{DECLARE,INIT} ->
MSPI_MEMMAP_*
- devicetree property xip-config -> memmap-config
Vendor HAL symbols (am_hal_mspi_xip_*) and DesignWare register names,
where XIP is the hardware documentation terminology, are unchanged.
The MSPI API is experimental, so no deprecated aliases are provided;
a migration guide entry is added in a separate commit. Add missing
Doxygen comments on new API symbols. Add missing SPDX header to the
nrf54h20dk code_relocation_nocopy overlay touched by this rename.
Fixes#104657
Signed-off-by: Richard Wheatley <richard.wheatley@ambiq.com>
The compat string is updated in device drivers to align with
changes in binding files.
Added depends on $(dt_compat_on_bus,$(DT_COMPAT_[DEVICE]),mspi)
to device Kconfig.
Signed-off-by: Swift Tian <swift.tian@ambiq.com>
Add a controller and PHY driver for the BL808 UHS PSRAM. The PHY read/write
eye is calibrated at boot by sweeping the DQS/DQ delay taps and latency, so
any supported rate works without per-rate constants. Add the devicetree
nodes and enable on the M1S Dock.
Signed-off-by: William Markezana <william.markezana@gmail.com>
Generic MSPI driver for the ISSI IS66/67WV Serial PSRAM family
(both wrapped-burst WVS and continuous WVR variants).
Implements MEMC read/write for bus-transaction access via MSPI.
When CONFIG_MSPI_XIP=y and xip-config is present in DT with
enable=true, also implements get_mem_base so the memcpy path
is used automatically on controllers with a memory-mapped
aperture.
Signed-off-by: Dhanoo Surasarang <dhanoo.surasarang@nordicsemi.no>
Drop duplicated HAL_XSPIM_Config fallback code from STM32 XSPI
flash, MSPI, and MEMC drivers.
With manager setup centralized in the common XSPIM driver and
explicit xspim devicetree nodes, XSPI consumer drivers no longer
need to configure XSPIM directly.
Assisted-by: GitHub Copilot:GPT-5.3-Codex west
Signed-off-by: Erwan Gouriou <erwan.gouriou@st.com>
Update hal_silabs to new HAL versions:
* SiSDK 2025.12.3
* WiSeConnect 4.0.2
This HAL update requires a minor change to the `memc` driver
for SiWx91x because an API has been renamed.
Signed-off-by: Aksel Skauge Mellbye <aksel.mellbye@silabs.com>
This commit adds support for APS256 and APS6408L in RLC/WLC
configuration. This includes a dedicated mapping for these
variants.
also this commit updates:
- Read/write length handling for APS256/APS6408L
- Vendor ID read sequence to support APS256/APS6408L
register behavior
Signed-off-by: Sara Touqan <zephyr@exalt.ps>
Signed-off-by: Sarah Younis <zephyr@exalt.ps>
Add memc_flexspi_apply_pinctrl() for configuring additional FlexSPI
port pins when init is skipped due to XIP, and memc_flexspi_update_lut()
for runtime LUT updates using a stack buffer to avoid XIP pointer
rejection.
Guard all irq_lock() calls with CONFIG_FLASH_MCUX_FLEXSPI_XIP so
non-XIP systems do not incur unnecessary interrupt latency.
Signed-off-by: Ruijia Wang <ruijia.wang@nxp.com>
shared_multi_heap_add expects the region parameter to be
a non-const parameter; if const is passed, it still discards
it, but generates warnings.
Signed-off-by: Krisztian Szilvasi <krisztian@atym.io>
Utilize a code spell-checking tool to scan for and correct spelling errors
in all files within:
- `drivers/interrupt_controller`
- `drivers/led_strip`
- `drivers/lora`
- `drivers/memc`
- `drivers/mfd`
Signed-off-by: Pisit Sawangvonganan <pisit@ndrsolution.com>
Implement a device driver for XSPI manager.
This allows to define the xspi controllers configuration that should
be applied towards the xspi IO ports:
- Muxed
- Swapped
- ...
Since its configuration has impact on final application location and
implies the deactivation of xspi clocks, it should be run only at fsbl
stage and not later.
Signed-off-by: Erwan Gouriou <erwan.gouriou@st.com>
Name the XSPI 1/2 depending on the stm32 series.
It could be mixed between XSPI or OCTOSPI depending
on the module HAL.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
If the clock device (i.e., RCC) failed to initialize, we have bigger
problems than trying to call clock_control_{off,on,configure} on it.
Don't bother checking to save some footprint.
Signed-off-by: Mathieu Choplain <mathieu.choplain-ext@st.com>
As per Zephyr coding guideline #59, "operands shall not be of an
inappropriate essential type". This makes sure boolean variables are
initialized with true/false, not 1/0.
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
Example DTS config comment is meant to help users of the
driver, with the PSRAM device tree configuration.
Signed-off-by: Nikhil Namjoshi <nikhilnamjoshi@google.com>
Tested:
Verified that reading and writing data to the PSRAM
with MCU's FlexSPI controller in Quad Mode, works as
expected.
Signed-off-by: Nikhil Namjoshi <nikhilnamjoshi@google.com>
Enable clock control by default for siwx91x SoCs. Moreover, most
drivers for siwx91x soc depend on clock control, but didn't declare
it.
Signed-off-by: Martin Hoff <martin.hoff@silabs.com>
Use the "zephyr-keep-sorted-start/stop" comment to have CI check
the alphabetical order of includes, to help reducing the chance
of conflicts while contributing drivers.
Signed-off-by: Josuah Demangeon <me@josuah.net>
Use STM32_CLOCK_INFO(), STM32_DT_INST_CLOCK_INFO(),
STM32_CLOCK_INFO_BY_NAME() and STM32_DT_INST_CLOCK_INFO_BY_NAME()
helper macros in STM32 drivers.
Using these macros ensure the clock division factor is properly
populated according to DT information. Prior these changes some
drivers only got the bus and bits position information and missed
the clock division information which is fine only when this division
factor information is 0.
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Avoid calling the HAL_XSPIM_Config function if the app is running
from flash in order to avoid locking since HAL_XSPIM_Config is once
turning off each XSPI instance when performing the configuration.
Signed-off-by: Alain Volmat <alain.volmat@foss.st.com>
The PSRAM could well be plugged to the XSPI2 instead of XSPI1
hence allow configuration of the IOPort and avoid forcing the
ChipSelect in order to allow working on both XSPI1 or XSPI2.
Signed-off-by: Alain Volmat <alain.volmat@foss.st.com>
Avoid copying the whole XSPI_HandleTypeDef structure into the
init function and use a pointer since the structure is already part
of the _data structure.
Signed-off-by: Alain Volmat <alain.volmat@foss.st.com>
For all STM32 drivers and SoC, replace the MODIFY_REG macro (defined in
the STM32 HAL) by stm32_reg_modify_bits defined in Zephyr.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
Enable this kconfig setting to force using a specific raw value for the
OVRDVAL field in the DLLCR registers.
This option gives more granularity than the 'data-valid-time' field in
the dts. The unit of 'data-valid-time' is nanoseconds while the unit of
OVRDVAL are raw delay cells.
Normally the 'data-valid-time' on any 'nxp,imx-flexspi-device' device
will set the OVRDVAL and OVRDEN fields in the DLLCR register
but works only when the 'rx-clock-source' is configured to '#0 External
input from DQS pad' and the frequency <= 100MHz.
Signed-off-by: Andre Heinemans <andre.heinemans@nxp.com>
In the original HAL, sl_si91x_psram_init() and sl_si91x_psram_uninit() were
also in charge of configuring the pinctrl and the clocks. A workaround
have been introduced to avoid change in pinctrl but they still changed the
clock configuration.
We definitely need to expose the clock configuration to Zephyr users. The
HAL has been patched to split the sl_si91x_psram_*init() function in
smaller pieces. So it is possible to configure the devic without changing
the clock or the pinctrl. Let's use these new functions.
Signed-off-by: Jérôme Pouiller <jerome.pouiller@silabs.com>
Memory APS6404L does not support address shift feature.
Since it is being configured for different platforms that uses this
memory, this is cauing an error while building.
Signed-off-by: Missael Maciel <davidmissael.maciel@nxp.com>
This patch fixes PSRAM initialization logic in x8 mode by ensuring that
the data line mode configuration accurately reflects the io-x16-mode
property specified in the device tree.
Signed-off-by: Arthur Gay <arthur.gay@marshmallow.kids>
