Added support to gicv3 driver to utilize the
extended SPI MMIO registers introduced in
GICv3.1 for the extended SPI range.
Documentation for the Extended Shared
Peripheral Interrupts extension can be found
in the ARM General Interrupt Controller
Architecture Specification:
https://developer.arm.com/documentation/ihi0069/latest/
Signed-off-by: Adam Openshaw <quic_adamo@quicinc.com>
In SMP, MPID is mybe not equal to cpu logic ID, so can't
use MPID to get rdist base address from gic_rdists[], this
patch get logic ID from arch_curr_cpu()->id, and
find current CPU's rdist base address from:
gic_rdists[cpu_logic_id]
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Add SMP support.
Note: there is still limitation that we rely on NUM CPUs.
And all cpus must be from 0,1,2 and ....
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Add basic driver for GIC V3 interrupt controller.
This implementation supports
- distributor, re-distributor and cpu interface initialization
- configuration and handling of SPI, PPI and SGI.
- V2 Legacy mode is not supported and uses system interface.
Current implementation supports GIC secure state only.
All interrupts are routed to Secure EL1 as 'irq' by configuring
them as Group1 Secure.
TODO:
- MPIDR based affinity routing setting.
- percpu redistributor probe
- message based SPI and SGI generation api
- EL1NS support. Legacy mode support.
- LPI/ITS is not supported.
Signed-off-by: Sandeep Tripathy <sandeep.tripathy@broadcom.com>
